Apparatus of offset voltage adjustment in input buffer

Patent metadata

Field	Value
Publication number	US-10153016-B2
Application number	US-201715702848-A
Country	US
Kind code	B2
Filing date	Sep 13, 2017
Priority date	Sep 20, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a first input node and a second input node, a switch that couples the first input node and the second input node in an active state and further decouples the first input node and the second input node in an inactive state, a control circuit that provides a signal causing the switch to be in the active state or an inactive state. The first input node of the input buffer is coupled to the input pad by a conductive wiring.

First claim

What is claimed is:

1. An apparatus comprising:
an input pad;
a first input buffer including a first input node and a second input node;
a conductive wiring configured to permanently couple between the input pad and the first input node of the first input buffer to provide a permanent electrical path between the input pad and the first input node of the first input buffer, and to couple an input signal from the input pad to the first input node; and
a first switch coupled to the first input node of the first input buffer to couple a reference voltage to the first input node of the first input buffer when the input signal from the input pad is at a floating state.

2. The apparatus of claim 1 , further comprising:
a reference voltage generator coupled to the second input node of the first input buffer and configured to generate a reference voltage.

3. The apparatus of claim 2 , wherein the first input buffer is configured to provide a signal responsive to a relative voltage that is a first voltage at the first input node relative to a second voltage at the second input node, and
wherein the first input buffer is configured to receive a test signal and further configured to adjust the relative voltage responsive to the test signal.

4. The apparatus of claim 1 , further comprising:
a second input buffer including a third input node and a fourth input node; and
a second switch configured to couple the input pad to the third input node of the second input buffer.

5. The apparatus of claim 4 , wherein the input pad is configured to provide at least a part of a command, and
wherein the second switch is configured to couple the input pad and the third input node of the second input buffer responsive to at least part of a command provided to the input pad.

6. The apparatus of claim 1 , further comprising an enable input pad, wherein the first switch is configured to couple the input pad and the second input node responsive to an enable signal provided to the enable input pad.

7. The apparatus of claim 6 , further comprising a reference voltage generator coupled to the second input node of the first input buffer and configured to generate a reference voltage,
wherein one of the reference voltage generator and the input pad is configured to provide the reference voltage to the first input node and the second input node responsive to the enable signal, and
wherein the other of the reference voltage generator and the input pad is at a floating state responsive to the enable signal.

8. An apparatus comprising:
an input pad;
a first input buffer including a first input node and a second input node, the first input node being permanently coupled to the input pad by a conductive wiring that provides a permanent electrical path between the first input node and the input pad and that couples an input signal from the input pad to the first input node; and
a first switch coupled between the first and second input nodes of the first input buffer to couple a reference voltage to the first input node of the first input buffer when the input signal from the input pad is at a floating state;
wherein the apparatus is configured to perform operations in a normal mode and a test mode, the test mode comprising a first phase and a second phase,
wherein the first switch is open in the normal mode; and
wherein the first switch is open in the first phase of the test mode and the first switch is closed responsive, at least in part, to a change of the test mode from the first phase to the second phase.

9. The apparatus of claim 8 , further comprising a control circuit configured to decouple the first input node and the second input node of the first input buffer in a first phase and couple the first input node and the second input node of the first input buffer in a second phase following to the first phase.

10. The apparatus of claim 9 , wherein the control circuit is configured to receive a first control signal from the input terminal pad in the first phase and send a second control signal to the first input buffer in the second phase, wherein the second control signal is produced correspondingly to the first signal.

11. The apparatus of claim 10 , wherein the first input buffer is configured to perform a voltage comparison between the first input node and the second input node and the voltage comparison is affected by an amount of an offset voltage of the first input buffer; and
wherein the amount of the offset voltage of the first input buffer is adjusted by the second control signal.

12. An apparatus comprising:
an input terminal;
an input buffer including a first input node coupled to the input terminal by a conductive wiring that provides a permanent electrical path between the input terminal and the first input node and that couples an input signal from the input terminal to the first input node, and further including a second input node and an output node;
a switch configured to couple the first input node and the second input node of the input buffer and to couple a reference voltage to the first input node of the input buffer when the input signal from the input terminal is at a floating state; and
a control circuit configured to decouple the first and second input nodes in a first phase and couple the first and second input nodes in a second phase following the first phase.

13. The apparatus of claim 12 , wherein the control circuit is configured to receive a first control signal from the input terminal in the first phase and send a second control signal to the input buffer in the second phase, wherein the second control signal is produced correspondingly to the first control signal.

14. The apparatus of claim 13 , wherein the input buffer is configured to perform a voltage comparison between the first input node and the second input node and the voltage comparison is affected by an amount of an offset voltage of the first input buffer; and
wherein the amount of the offset voltage of the first input buffer is adjusted by the second control signal.

15. The apparatus of claim 12 , further comprising a reference voltage generator configured to supply a reference voltage to the second input node of the input buffer in each of the first and second phases.

16. The apparatus of claim 12 , further comprising a reference voltage generator coupled to the second input node of the input buffer and configured not to supply any voltages to the second input node in the second phase;
wherein the input terminal is configured to receive a reference voltage externally in the second phase.

17. The apparatus of claim 12 , wherein the control circuit is further configured to externally output an output signal from the input buffer via a DQ terminal in a third phase following the second phase.

Assignees

• Micron Technology Inc

Inventors

• Okuma Sadayuki

Classifications

• G11C7/1087

  Data input latches · CPC title

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• G11C7/1084 Primary

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title