Differential reference voltage buffer

Patent metadata

Field	Value
Publication number	US-11320846-B2
Application number	US-201817258159-A
Country	US
Kind code	B2
Filing date	Dec 13, 2018
Priority date	Aug 23, 2018
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

The present disclosure provides a differential reference voltage buffer, including: a buffer stage, including at least a first transistor and a second transistor; a control circuit, connected with the buffer stage and forming a negative feedback structure for generating a differential reference voltage; a current compensation circuit for compensating a resistive load current of the control circuit; and a drive stage for generating an output differential reference voltage. The differential reference voltage is generated according to an external input reference voltage and a common mode input voltage. The common mode voltage can be set separately, so that the flexibility is high. The current generated by a resistive network in the control circuit is compensated by the current compensation circuit, so that the current of a follow device in the buffer stage is not influenced by the control circuit, thereby generating a differential reference voltage with high accuracy output.

First claim

The invention claimed is:

1. A differential reference voltage buffer, comprising:
a buffer stage, comprising at least a first transistor and a second transistor;
a control circuit, connected with the buffer stage to form a negative feedback structure for generating a differential reference voltage; the control circuit comprises at least a first operational amplifier, a first resistor, a second resistor, and a common mode feedback circuit;
the first operational amplifier includes two input ends, a first input end of the first operational amplifier is connected with a source of the first transistor and the common mode feedback circuit through the first resistor, and a second input end of the first operational amplifier is connected with a source of the second transistor and the common mode feedback circuit through the second resistor;
a current compensation circuit, to compensate for a resistive load current of the control circuit; and
a drive stage, to generate an output differential reference voltage.

2. The differential reference voltage buffer according to claim 1 , wherein the current compensation circuit comprises a second operational amplifier, a third operational amplifier, a third resistor and a fourth resistor;
the second operational amplifier includes two input ends, a first input end of the second operational amplifier is connected with the source of the first transistor, and a second input end of the second operational amplifier is connected with a signal ground through the third resistor;
the third operational amplifier includes two input ends, a first input end of the third operational amplifier is connected with the source of the second transistor, and a second input end of the third operational amplifier is connected with an input voltage Vref through the fourth resistor.

3. The differential reference voltage buffer according to claim 2 , wherein the current compensation circuit further comprises a third transistor and a fourth transistor; the first input end of the second operational amplifier is connected with a current treatment end of the third transistor; the second input end of the second operational amplifier is connected with a current treatment end of the fourth transistor, and an output end of the second operational amplifier is connected with a gate of the third transistor and a gate of the fourth transistor, respectively.

4. The differential reference voltage buffer according to claim 2 , wherein the current compensation circuit further comprises a fifth transistor and a sixth transistor; the first input end of the third operational amplifier is connected with a current treatment end of the fifth transistor, the second input end of the third operational amplifier is connected with a current treatment end of the sixth transistor, and an output end of the third operational amplifier is connected to a gate of the fifth transistor and a gate of the sixth transistor, respectively.

5. The differential reference voltage buffer according to claim 1 , wherein the control circuit further comprises a fifth resistor and a sixth resistor; the first input end of the first operational amplifier is connected with a signal ground through the fifth resistor, and the second input end of the first operational amplifier is connected with an input voltage Vref through the sixth resistor.

6. The differential reference voltage buffer according to claim 1 , wherein the common mode feedback circuit comprises a fourth operational amplifier, a seventh resistor and an eighth resistor;
one end of the seventh resistor and one end of the eighth resistor are two input ends of a detection level of the common mode feedback circuit, the other end of the seventh resistor and the other end of the eighth resistor are respectively connected with a first input end of the fourth operational amplifier; a second input end of the fourth operational amplifier is a common mode level input end of the common mode feedback circuit, and an output end of the fourth operational amplifier is an output end of the common mode feedback circuit.

7. The differential reference voltage buffer according to claim 6 , wherein the first operational amplifier comprises an output end connected with a gate of the first transistor; a gate of the second transistor is connected with the output end of the common mode feedback circuit; the first transistor and the second transistor form a source follower and share a bias current.

8. The differential reference voltage buffer according to claim 6 , wherein the first operational amplifier includes two output ends and a common mode feedback input end; a first output end of the first operational amplifier is connected with a gate of the first transistor; a second output end of the first operational amplifier is connected with a gate of the second transistor; the common mode feedback input end is connected with the output end of the common mode feedback circuit; the first transistor and the second transistor are respectively connected with the control circuit and form a source negative feedback mode.

9. The differential reference voltage buffer according to claim 2 , wherein the first input end of the second operational amplifier is a negative input end, the second input end of the second operational amplifier is a positive input end; the third transistor and the fourth transistor are PMOS transistors; a current treatment end of the third transistor is a drain of the third transistor, and a current treatment end of the fourth transistor is a drain of the fourth transistor.

10. The differential reference voltage buffer according to claim 2 , wherein the first input end of the second operational amplifier is a positive input end, the second input end of the second operational amplifier is a negative input end; the third transistor and the fourth transistor are NMOS transistors; a current treatment end of the third transistor is a source of the third transistor, and a current treatment end of the fourth transistor is a source of the fourth transistor.

11. The differential reference voltage buffer according to claim 2 , wherein the first input end of the third operational amplifier is a negative input end, the second input end of the third operational amplifier is a positive input end; the fifth transistor and the sixth transistor are NMOS transistors; a current treatment end of the fifth transistor is a drain of the fifth transistor, and a current treatment end of the sixth transistor is a drain of the sixth transistor.

12. The differential reference voltage buffer according to claim 2 , wherein the first input end of the third operational amplifier is a positive input end, the second input end of the third operational amplifier is a negative input end; the fifth transistor and the sixth transistor are PMOS transistors; a current treatment end of the fifth transistor is a source of the fifth transistor, and a current treatment end of the sixth transistor is a source of the sixth transistor.

13. The differential reference voltage buffer according to claim 5 , wherein a resistance value of the third resistor is the sum of a resistance value of the first resistor and a resistance value of the fifth resistor; a resistance value of the fourth resistor is the sum of a resistance value of the second resistor and a resistance value of the sixth resistor.

14. The differential reference voltage buffer according to claim 6 , wherein the current compensation circuit further comprises a ninth resistor; one end of the ninth resistor is connected with the first input end of the second operational amplifier, and the other end of the ninth resistor is connected with th

Assignees

• No 24 Research Institute Of China Electronics Tech Group Corporation

Inventors

• Wang Yan
• Hu Gangyi
• Liu Tao
• Wang Jian'An
• Xu Daiguo
• Chen Guangbing
• Fu Dongbing

Classifications

• H03F2203/45138

  Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers · CPC title

• H03F3/45973

  by using a feedback circuit · CPC title

• G05F1/461 Primary

  using an operational amplifier as final control device · CPC title

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• G05F1/468

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title