Digital clamp for state retention

Patent metadata

Field	Value
Publication number	US-9484917-B2
Application number	US-201213718372-A
Country	US
Kind code	B2
Filing date	Dec 18, 2012
Priority date	Dec 18, 2012
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is operable to adjust the second power supply when the apparatus enters a low power mode.

First claim

We claim:

1. An apparatus comprising:
a clamp coupled between a first power supply and a second power supply, wherein the clamp includes a plurality of transistors;
a circuit to operate with the second power supply; and
a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode, comprising:
a comparator to compare the second power supply with a reference, wherein the reference is received at the positive terminal of the comparator and the second power supply is received at the negative terminal of the comparator; and
a counter to count up when the second power supply is higher than the reference and to count down when the second power supply is lower than the reference, wherein a higher count of the counter corresponds to more transistors of the clamp being turned off.

2. The apparatus of claim 1 wherein the control unit comprises:
a decoder to convert an output of the counter to a digital control signal for adjusting the second power supply via the clamp.

3. The apparatus of claim 2 , wherein the plurality of transistors are p-type devices having their source nodes coupled to the first power supply and drain nodes coupled to the second power supplies, wherein the digital control signal of the decoder is provided to the clamp for controlling the clamp.

4. The apparatus of claim 2 , wherein the decoder to generate a thermometer coded digital control signal or a binary weighted digital control signal.

5. The apparatus of claim 1 , wherein the circuit comprises combinational logic units and sequential units.

6. The apparatus of claim 1 , wherein the low power mode is a sleep mode.

7. The apparatus of claim 1 , wherein the plurality of the transistors have same conductance characteristics.

8. The apparatus of claim 1 , wherein the clamp comprises at least of three transistors.

9. The apparatus of claim 1 , wherein all of the plurality of the transistors are turned on during a normal power mode.

10. A system comprising:
a memory;
a processor, coupled to the memory, the processor including:
an apparatus comprising:
a clamp coupled between a first power supply and a second power supply, wherein the clamp includes a plurality of transistors;
a circuit to operate with the second power supply; and
a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode, comprising:
a comparator to compare the second power supply with a reference, wherein the reference is received at the positive terminal of the comparator and the second power supply is received at the negative terminal of the comparator; and
a counter to count up when the second power supply is higher than the reference and to count down when the second power supply is lower than the reference, wherein a higher count of the counter corresponds to more transistors of the clamp being turned off; and

a wireless interface for allowing the processor to communicate with another device.

11. The system of claim 10 , wherein the control unit comprises:
a decoder to convert an output of the counter to a digital control signal for adjusting the second power supply via the clamp.

Assignees

• Raychowdhury Arijit
• Augustine Charles
• Tschanz James W
• De Vivek K
• Intel Corp

Inventors

• Raychowdhury Arijit
• Augustine Charles
• Tschanz James W
• De Vivek K

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• H03K3/0377

  Bistables with hysteresis, e.g. Schmitt trigger (non-regenerative amplitude discriminators G01R19/165) · CPC title

• H03K19/0008 Primary

  Arrangements for reducing power consumption · CPC title

• H03K19/0016 Primary

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title