Electrostatic discharge with parasitic compensation

Patent metadata

Field	Value
Publication number	US-11316340-B2
Application number	US-201916526627-A
Country	US
Kind code	B2
Filing date	Jul 30, 2019
Priority date	Jul 30, 2019
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A circuit for preventing failure of a device includes a first rail, electrostatic discharge (ESD) protection circuitry, a second rail, an ESD switching circuitry, biasing circuitry, and a signal limiter. The first rail is for one or more first electrical components formed in a first portion of a substrate. The second rail is for one or more second electrical components formed in a second portion of the substrate. The first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor. The biasing circuitry is configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switching circuitry is switched on. The signal limiter electrically couples to the first rail and the emitter of the parasitic transistor.

First claim

The invention claimed is:

1. A circuit comprising:
a first rail for one or more first electrical components formed in a first portion of a substrate;
electrostatic discharge (ESD) protection circuitry electrically coupled between the first rail and a reference rail, wherein the ESD protection circuitry is configured to generate an electrically conductive path between the first rail and the reference rail during an ESD event;
a second rail for one or more second electrical components formed in a second portion of the substrate, wherein the first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor;
an ESD switching circuitry electrically coupled between the second rail and the reference rail, wherein the ESD switching circuitry is configured to switch on during the ESD event to generate an electrically conductive path between the second rail and the reference rail;
biasing circuitry configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switching circuitry is switched on; and
a signal limiter configured to electrically couple the first rail and the emitter of the parasitic transistor.

2. The circuit of claim 1 , wherein the signal limiter comprises a diode comprising an anode electrically coupled to the first rail and a cathode electrically coupled to the emitter of the parasitic transistor.

3. The circuit of claim 1 , wherein the signal limiter comprises a resistive element comprising a first node electrically coupled to the first rail and a second node electrically coupled to the emitter of the parasitic transistor.

4. The circuit of claim 1 ,
wherein the first portion of the substrate comprises a first N-type layer; and
wherein the second portion of the substrate comprises a second N-type layer.

5. The circuit of claim 4 , wherein the first N-type layer and the second N-type layer are separated by deep trench isolation.

6. The circuit of claim 4 , wherein the first N-type layer and the second N-type layer are formed on a common P-type layer.

7. The circuit of claim 1 , wherein the ESD protection circuitry comprises a diode comprising an anode electrically coupled to the reference rail and a cathode electrically coupled to the first rail.

8. The circuit of claim 7 , wherein the diode is a Zener diode.

9. The circuit of claim 7 , wherein the parasitic transistor is a first parasitic transistor and wherein the diode comprises a second parasitic transistor, the second parasitic transistor comprising an emitter electrically coupled to the first rail, a collector electrically coupled to the emitter of the first parasitic transistor, and a base electrically coupled to the reference rail.

10. The circuit of claim 1 , wherein the ESD protection circuitry comprises a switching element comprising a first node electrically coupled to the reference rail and a second node electrically coupled to the first rail and wherein, to generate the electrically conductive path between the first rail and the reference rail during the ESD event, the switching element is configured to switch on.

11. The circuit of claim 1 ,
wherein when the ESD protection circuitry generates the electrically conductive path between the first rail and the reference rail during the ESD event, the ESD protection circuitry drives voltage at the first rail to be less than voltage at the reference rail; and
wherein the biasing circuitry is configured to output the bias voltage to be greater than voltage at the reference rail during the ESD event.

12. The circuit of claim 1 , wherein the ESD switching circuitry comprises:
a pass element comprising a control node, a first node electrically coupled to the second rail, and a second node electrically coupled to the reference rail.

13. The circuit of claim 12 , wherein the biasing circuitry comprises:
a diode comprising an anode and cathode, the cathode of the diode being electrically coupled to the emitter of the parasitic transistor; and
a source-follower element comprising a control node electrically coupled to the control node of the pass element, a first node electrically coupled to the second rail, and a second node electrically coupled to the anode of the diode.

14. The circuit of claim 12 , wherein the ESD switching circuitry comprises:
triggering circuitry comprising one or more triggering elements arranged in a series string, wherein a first end of the series string is electrically coupled to the second rail and a second end of the series string is electrically coupled to the control node of the pass element; and
a resistance element comprising a first node electrically coupled to the control node of the pass element and a second node electrically coupled to the reference rail.

15. The circuit of claim 12 , wherein the ESD switching circuitry comprises an RC trigger element.

16. The circuit of claim 1 , wherein the parasitic transistor is a first parasitic transistor, wherein the biasing circuitry is further configured to output, via a second diode, the bias voltage at an emitter of a second parasitic transistor when the ESD switching circuitry is switched on.

17. The circuit of claim 1 ,
wherein the ESD switching circuitry comprises a switching element configured to switch on during the ESD event; or
wherein the ESD switching circuitry comprises a PN-type device with a P-junction electrically coupled to the reference rail.

18. The circuit of claim 1 ,
wherein the first rail is a supply rail, the second rail is a supply rail, or the first rail and the second rail are supply rails; or
wherein the first rail is an Input/Output (I/O) rail, the second rail is an I/O rail, or the first rail and the second rail are I/O rails.

19. A method comprising:
generating, by electrostatic discharge (ESD) protection circuitry, an electrically conductive path between a first rail and a reference rail during an ESD event, wherein the first rail is configured for one or more first electrical components formed in a first portion of a substrate;
switching-on an ESD switching circuitry electrically coupled between a second rail and the reference rail during the ESD event to generate an electrically conductive path between the second rail and the reference rail, wherein the second rail is configured for one or more second electrical components formed in a second portion of the substrate, wherein the first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor; and
outputting a bias voltage at the emitter of the parasitic transistor when the ESD switching circuitry is switched-on, wherein a signal limiter electrically couples the first rail and the emitter of the parasitic transistor.

20. A system comprising:
a reference rail;
one or more first electrical components formed in a first portion of a substrate;
a first rail for the one or more first electrical components;
electrostatic discharge (ESD) protection circuitry electrically coupled between the first rail and the reference rail, wherein the ESD protection circuitry is configured to generate an electrically conductive path between the first rail and the reference rail during an ESD event;
one or more second electrical components formed in a second portion of the substrate, wherein the first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector

Assignees

• Infineon Technologies Ag

Inventors

• Glaser Ulrich

Classifications

• H10D89/921

  characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title

• H10D89/811

  using FETs as protective elements · CPC title

• H10D89/711

  using bipolar transistors as protective elements · CPC title

• H10D89/611 Primary

  using diodes as protective elements · CPC title

• H10D84/403

  Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors · CPC title