Noise-tolerant active clamp with ESD protection capability in power up mode

Patent metadata

Field	Value
Publication number	US-9413166-B2
Application number	US-201414162410-A
Country	US
Kind code	B2
Filing date	Jan 23, 2014
Priority date	Jan 23, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A circuit is described comprising electrostatic discharge (ESD) protection circuitry, keep-off circuitry and ESD detection circuitry. When the ESD detection circuitry detects an ESD event, the ESD detection circuitry is configured to both enable the ESD protection circuitry and disable the keep-off circuitry.

First claim

The invention claimed is:

1. A circuit comprising:
electrostatic discharge (ESD) protection circuitry;
keep-off circuitry;
ESD detection circuitry configured to enable the ESD protection circuitry and disable the keep-off circuitry when the ESD detection circuitry detects an ESD event; and
keep-off-control circuitry, wherein the ESD detection circuitry is configured to disable the keep-off circuitry by means of the keep-off-control circuitry in response to the ESD detection circuitry detecting the ESD event while the circuit is operating in a powered on state.

2. The circuit of claim 1 , wherein the ESD detection circuitry is further configured to disable the ESD protection circuitry and enable the keep-off circuitry by means of the keep-off-control circuitry when the ESD detection circuitry does not detect the ESD event.

3. The circuit of claim 2 , wherein the ESD detection circuitry is further configured to disable the ESD protection circuitry and enable the keep-off circuitry by means of the keep-off-control circuitry when the ESD detection circuitry does not detect the ESD event and the circuit is operating in a powered on state.

4. The circuit of claim 1 , wherein the keep-off-control circuitry comprises a switch, and wherein the ESD detection circuitry is configured not to enable the ESD protection circuitry by means of the keep-off-control circuitry by controlling the switch when the keep-off circuitry is enabled.

5. The circuit of claim 1 , wherein the keep-off-control circuitry comprises a switch, and wherein the ESD detection circuitry is configured to enable the ESD protection circuitry by means of the keep-off-control circuitry by controlling the switch to disable the keep-off circuitry.

6. The circuit of claim 1 , wherein the ESD detection circuitry is configured to detect the ESD event when the ESD detection circuitry determines that a voltage at an input of the circuit satisfies at least one voltage level threshold criterion or at least one frequency threshold criterion.

7. The circuit of claim 1 , wherein the ESD detection circuitry is configured to detect a non-ESD event and not detect the ESD event when the ESD detection circuitry detects a voltage at an input of the circuit that does not satisfy at least one voltage level threshold criterion or at least one frequency threshold criterion.

8. The circuit of claim 1 , wherein the ESD detection circuitry comprises a diode trigger chain for enabling the ESD protection circuitry.

9. The circuit of claim 8 , wherein the ESD detection circuitry is configured to detect the ESD event and enable the ESD protection circuitry when a voltage across the diode trigger chain exceeds a breakdown voltage associated with the diode trigger chain and satisfies a frequency threshold based on a time constant associated with the ESD detection circuitry.

10. The circuit of claim 9 , wherein the ESD detection circuitry comprises at least one capacitor and at least one resistor and the time constant associated with the ESD detection circuitry is based on the at least one capacitor and the at least one resistor.

11. The circuit of claim 9 , wherein the time constant associated with the ESD detection circuitry is based on a parasitic capacitance associated with one or more elements of the ESD detection circuitry.

12. A method comprising:
detecting, by electrostatic discharge (ESD) detection circuitry of a circuit, a voltage event at an input of the circuit;
determining, by the ESD detection circuitry, whether the voltage event at the input is indicative of an ESD event; and
responsive to determining that the voltage event is indicative of an ESD event:
disabling, by the ESD detection circuitry of the circuit, keep-off circuitry of the circuit in response to detecting an ESD event while the circuit is operating in a powered on state; and
enabling, by the ESD detection circuitry of the circuit and by means of keep-off-control circuitry of the circuit, ESD protection circuitry of the circuit.

13. The method of claim 12 , further comprising:
enabling the ESD protection circuitry of the circuit when the circuit is operating in a powered off state.

14. The method of claim 12 , further comprising:
responsive to determining that the voltage event is not indicative of an ESD event:
enabling, by the ESD detection circuitry of the circuit and by means of keep-off-control circuitry, the keep-off circuit; and
disabling, by the ESD detection circuitry of the circuit, the ESD protection circuit.

15. The method of claim 12 , wherein determining whether the voltage event is indicative of an ESD event comprises at least one of determining, by the ESD detection circuitry of the circuit, whether a voltage level associated with the voltage event exceeds a breakdown voltage associated with a diode trigger chain of the ESD detection circuitry, or
determining, by the ESD detection circuitry of the circuit, whether a frequency level associated with the voltage event satisfies a frequency threshold.

16. The method of claim 15 , wherein the frequency threshold is based on a time constant associated with the ESD detection circuitry.

17. A system comprising:
means for detecting a voltage event at an input of the circuit;
means for determining whether the voltage event at the input is indicative of an ESD event; and
means for disabling keep-off circuitry of the circuit in response to determining that the voltage event is indicative of the ESD event while the system is operating in a powered on state; and
means for enabling ESD protection circuitry of the circuit in response to determining that the voltage event is indicative of the ESD event.

Assignees

• Infineon Technologies Ag

Inventors

• Rupp Andreas
• Cao Yiqun
• Glaser Ulrich

Classifications

• H02H9/04 Primary

  responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T) · CPC title