Method of forming a device with planar split gate non-volatile memory cells, high voltage devices and FinFET logic devices

Patent metadata

Field	Value
Publication number	US-11315940-B2
Application number	US-202117151944-A
Country	US
Kind code	B2
Filing date	Jan 19, 2021
Priority date	Sep 21, 2020
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A method of forming memory cells, HV devices and logic devices on a substrate, including recessing the upper surface of the memory cell and HV device areas of the substrate, forming a polysilicon layer in the memory cell and HV device areas, forming first trenches through the first polysilicon layer and into the silicon substrate in the memory cell and HV device areas, filling the first trenches with insulation material, forming second trenches into the substrate in the logic device area to form upwardly extending fins, removing portions of the polysilicon layer in the memory cell area to form floating gates, forming erase and word line gates in the memory cell area, HV gates in the HV device area, and dummy gates in the logic device area from a second polysilicon layer, and replacing the dummy gates with metal gates that wrap around the fins.

First claim

What is claimed is:

1. A method of forming a device, comprising:
providing a silicon substrate with an upper surface and having first, second and third areas;
recessing the upper surface in the first and second areas of the substrate, but not in the third area of the substrate;
forming a first polysilicon layer over and insulated from the upper surface in the first and second areas;
forming first trenches through the first polysilicon layer and into the silicon substrate in the first and second areas but not in the third area, using at least a first silicon etch;
filling the first trenches with insulation material; after the filling of the first trenches, forming second trenches into the silicon substrate in the third area using at least a second silicon etch to form an upwardly extending fin of the silicon substrate having a pair of side surfaces extending up and terminating at a top surface;
after the forming of the fin, forming a pair of blocks of material over the first polysilicon layer in the first area; removing portions of the first polysilicon layer in the first area to form a pair of floating gates of the first polysilicon layer each disposed under one of the pair of blocks of material;
performing a first implantation to form a first source region in the silicon substrate in the first area between the pair of floating gates;
forming a second polysilicon layer over the silicon substrate in the first, second and third areas;
removing portions of the second polysilicon layer to form:
a first polysilicon block of the second polysilicon layer disposed over and insulated from the first source region in the first area,
a second polysilicon block of the second polysilicon layer disposed over and insulated from the silicon substrate and adjacent one of the pair of floating gates in the first area,
a third polysilicon block of the second polysilicon layer disposed over and insulated from the silicon substrate and adjacent another one of the pair of floating gates in the first area,
a fourth polysilicon block of the second polysilicon layer disposed over and insulated from the silicon substrate in the second area, and
a fifth polysilicon block of the second polysilicon layer disposed over and insulated from the pair of side surfaces and the top surface of the silicon fin in the third area;

performing one or more implantations to form:
a first drain region in the first area of the substrate adjacent the second polysilicon block,
a second drain region in the first area of the substrate adjacent the third polysilicon block,
a second source region in the second area of the substrate adjacent the fourth polysilicon block,
a third drain region in the second area of the substrate adjacent the fourth polysilicon block,
a third source region in the fin adjacent the fifth polysilicon block, and
a fourth drain region in the fin adjacent the fifth polysilicon block;

removing the fifth polysilicon block;
forming a layer of high K material along the pair of side surfaces and the top surface of the fin in the third area; and
forming a block of metal material on the layer of high K material in the third area so that the block of metal extends along and is insulated from the pair of side surfaces and the top surface of the fin.

2. The method of claim 1 , wherein the pair of blocks of material are formed of polysilicon and are insulated from the pair of floating gates.

3. The method of claim 2 , wherein the pair of blocks of material are insulated from the pair of floating gates by an oxide-nitride-oxide layer.

4. The method of claim 1 , wherein the pair of blocks of material are formed of an insulation material.

5. The method of claim 1 , the forming of the second trenches comprises:
forming a layer of material over the upper surface in the third area;
forming third trenches in the layer of material;
forming spacers of material in the third trenches;
removing the layer of material; and
performing the second silicon etch in portions of the silicon substrate between the spacers of material.

6. The method of claim 1 , wherein the forming of the third source region and the fourth drain region comprises:
before removing the fifth polysilicon block, epitaxially growing material on the fin adjacent to the fifth polysilicon block, wherein the third source region and the fourth drain regions are formed in the epitaxially grown material.

7. The method of claim 1 , wherein the second and third polysilicon blocks are insulated from the upper surface of the substrate by insulation material having a thickness that is less than a thickness of insulation material insulating the floating gates from the upper surface.

8. The method of claim 1 , wherein the fourth polysilicon block is insulated from the upper surface of the substrate by insulation material having a thickness that is different than a thickness of insulation material insulating the floating gates from the upper surface.

9. The method of claim 1 , wherein the first trenches extend deeper into the substrate than do the second trenches.

10. The method of claim 1 , wherein the second trenches extend deeper into the substrate than do the first trenches.

Assignees

• Silicon Storage Tech Inc

Inventors

• Wang Chunming
• Song guo xiang
• Xing leo
• Sun Jack
• Liu Xian
• Do Nhan

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title