Split gate non-volatile flash memory cell having metal gates and method of making same

Patent metadata

Field	Value
Publication number	US-9972630-B2
Application number	US-201615295022-A
Country	US
Kind code	B2
Filing date	Oct 17, 2016
Priority date	Nov 3, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

First claim

What is claimed is:

1. A method of forming a memory device, comprising:
forming spaced apart first source and first drain regions in a memory cell area of a silicon substrate, with a first channel region of the silicon substrate extending there between;
forming a conductive floating gate disposed over and insulated from a first portion of the first channel region that is adjacent the first source region;
forming a conductive word line gate disposed over and insulated from a second portion of the first channel region that is adjacent the first drain region;
forming a conductive control gate disposed over and insulated from the floating gate;
forming a conductive erase gate disposed over and insulated from the first source region;
forming a protective layer of material over the floating gate, the control gate, the erase gate and the word line gate;
forming an upwardly extending silicon fin in a logic device area of the silicon substrate by removing portions of the silicon substrate in the logic device area, wherein:
the silicon fin includes a pair of side surfaces extending up and terminating at a top surface, and
the forming of the upwardly extending silicon fin is performed after the forming of the floating gate, the control gate, the source region, the erase gate, the word line gate and the protective layer;

forming a conductive logic gate disposed over and insulated from the top surface, and disposed laterally adjacent to and insulated from the pair of side surfaces; and
forming spaced apart second source and second drain regions in the logic device area of silicon substrate with a second channel region of the silicon substrate extending there between, wherein the second channel region extends along the top surface and the pair of side surfaces.

2. The method of claim 1 , further comprising:
removing the protective layer after the forming of the silicon fin and the logic gate.

3. The method of claim 2 , wherein the forming of the first source region is performed before the forming of the protective layer, and the forming of the first drain region is performed after the removing of the protective layer.

4. The method of claim 2 , further comprising:
performing an etch to reduce a width of the word line gate after the removing of the protective layer.

5. The method of claim 4 , wherein the forming of the first drain region is performed after the performing of the etch.

6. The method of claim 1 , wherein the forming of the floating gate and the forming of the control gate comprise:
forming a first conductive layer over and insulated from the memory cell area of the silicon substrate;
forming a second conductive layer over and insulated from the first conductive layer in the memory cell area;
etching the second conductive layer to form a block of the second conductive layer over the first conductive layer; and
etching the first conductive layer to form a block of the first conductive layer between the substrate and the block of the second conductive layer;
wherein the block of the second conductive layer is the control gate and the block of the first conductive layer is the floating gate.

7. The method of claim 1 , wherein the conductive logic gate is insulated from the top surface and from the pair of side surfaces by a layer of high K material.

8. The method of claim 2 , wherein the conductive logic gate is formed of metal.

9. The method of claim 1 , wherein the word line gate is insulated from the second portion of the first channel region by a layer of high K material.

10. The method of claim 1 , wherein the word line gate is insulated from the second portion of the first channel region by a layer of high K material and a layer of oxide.

Assignees

• Silicon Storage Tech Inc

Inventors

• Su Chien-Sheng
• Zhou Feng
• Yang Jeng-Wei
• Tran Hieu Van
• Do Nhan

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H01L29/42328

  Electricity · mapped topic

• H01L29/788

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic