Two transistor FinFET-based split gate non-volatile floating gate flash memory and method of fabrication

Patent metadata

Field	Value
Publication number	US-10312247-B1
Application number	US-201815933124-A
Country	US
Kind code	B1
Filing date	Mar 22, 2018
Priority date	Mar 22, 2018
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A non-volatile memory cell formed on a semiconductor substrate having an upper surface with an upwardly extending fin with opposing first and second side surfaces. First and second electrodes are in electrical contact with first and second portions of the fin. A channel region of the fin includes portions of the first and second side surfaces that extend between the first and second portions of the fin. A floating gate extends along the first side surface of a first portion of the channel region, where no portion of the floating gate extends along the second side surface. A word line gate extends along the first and second side surfaces of a second portion of the channel region. A control gate is disposed over the floating gate. An erase gate has a first portion disposed laterally adjacent to the floating gate and a second portion disposed vertically over the floating gate.

First claim

The invention claimed is:

1. A non-volatile memory cell comprising:
a semiconductor substrate having an upper surface with an upwardly extending fin that includes first and second side surfaces that oppose each other and an upwardly extending second fin that includes third and fourth side surfaces that oppose each other;
a first electrode in electrical contact with a first portion of the fin;
a second electrode in electrical contact with a second portion of the fin, wherein the first and second portions of the fin are spaced apart from each other such that a channel region of the fin includes portions of the first and second side surfaces and extends between the first and second portions of the fin;
a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first side surface, wherein no portion of the floating gate extends along the second side surface, wherein at least a portion of the floating gate is disposed between the fin and the second fin and extends along and is insulated from the third side surface, and wherein no portion of the floating gate extends along the fourth side surface;
a word line gate that extends along a second portion of the channel region, wherein the word line gate extends along and is insulated from the first and second side surfaces;
a control gate disposed over and insulated from the floating gate;
an erase gate having a first portion disposed laterally adjacent to and insulated from the floating gate and a second portion disposed vertically over and insulated from the floating gate.

2. The non-volatile memory cell of claim 1 , wherein no conductive gate is disposed along and insulated from a portion of the second side surface that is opposite to a portion of the first side surface along which the floating gate extends.

3. The non-volatile memory cell of claim 1 , wherein the word line gate includes a metal material, and wherein the word line gate is insulated from the first and second side surfaces by a high K insulation material.

4. The non-volatile memory cell of claim 1 , wherein the control gate and the erase gate each are disposed vertically over the fin.

5. The non-volatile memory cell of claim 1 , wherein the first and second portions of the fin each have a width that is greater than a width of the channel region of the fin.

6. The non-volatile memory cell of claim 1 , wherein the first and second portions of the fin each have a height that is greater than a height of the channel region of the fin.

7. The non-volatile memory cell of claim 1 , wherein the first electrode extends along the first and second side surfaces of the first portion of the fin, and wherein the second electrode extends along the first and second side surfaces of the second portion of the fin.

8. The non-volatile memory cell of claim 1 , wherein the floating gate has a rectangular vertical cross section.

9. The non-volatile memory cell of claim 1 , wherein the floating gate has a U-shape vertical cross section.

10. The non-volatile memory cell of claim 3 , wherein the floating gate, the control gate and the erase gate each include polysilicon material.

11. The non-volatile memory cell of claim 10 , wherein the first and second electrodes each include a metal material.

12. The non-volatile memory cell of claim 9 , wherein the control gate includes a lower portion that extends into the U-shape vertical cross section of the floating gate.

13. A method of forming a non-volatile memory cell comprising:
forming trenches into an upper surface of a semiconductor substrate so that the upper surface includes an upwardly extending fin that includes first and second side surfaces that oppose each other and an upwardly extending second fin that includes third and fourth side surfaces that oppose each other;
forming a first electrode in electrical contact with a first portion of the fin;
forming a second electrode in electrical contact with a second portion of the fin, wherein the first and second portions of the fin are spaced apart from each other such that a channel region of the fin includes portions of the first and second side surfaces and extends between the first and second portions of the fin;
forming a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first side surface, wherein no portion of the floating gate extends along the second side surface, wherein at least a portion of the floating gate is disposed between the fin and the second fin and extends along and is insulated from the third side surface, and wherein no portion of the floating gate extends along the fourth side surface;
forming a word line gate that extends along a second portion of the channel region, wherein the word line gate extends along and is insulated from the first and second side surfaces;
forming a control gate disposed over and insulated from the floating gate;
forming an erase gate having a first portion disposed laterally adjacent to and insulated from the floating gate and a second portion disposed vertically over and insulated from the floating gate.

14. The method of claim 13 , wherein no conductive gate is disposed along and insulated from a portion of the second side surface that is opposite to a portion of the first side surface along which the floating gate extends.

15. The method of claim 13 , wherein the word line gate includes a metal material, and wherein the word line gate is insulated from the first and second side surfaces by a high K insulation material.

16. The method of claim 13 , wherein the floating gate, the control gate and the erase gate each include polysilicon material.

17. The method of claim 13 , wherein the control gate and the erase gate are each disposed vertically over the fin.

18. The method of claim 13 , wherein the first and second portions of the fin each have a width and a height that is greater than a width and a height respectively of the channel region of the fin.

19. The method of claim 13 , wherein the first electrode extends along the first and second side surfaces of the first portion of the fin, and wherein the second electrode extends along the first and second side surfaces of the second portion of the fin.

20. The method of claim 13 , wherein the floating gate has a rectangular vertical cross section.

21. The method of claim 13 , wherein the floating gate has a U-shape vertical cross section.

22. The method of claim 16 , wherein the first and second electrodes each include a metal material.

23. The method of claim 21 , wherein the control gate includes a lower portion that extends into the U-shape vertical cross section of the floating gate.

Assignees

• Silicon Storage Tech Inc

Inventors

• Jourba Serguei
• Decobert Catherine
• Zhou Feng
• Kim Jinho
• Liu Xian
• Do Nhan

Classifications

• H01L29/7838

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic

• H01L29/7883

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic