Methods of forming microvias with reduced diameter

Patent metadata

Field	Value
Publication number	US-11315890-B2
Application number	US-202017006277-A
Country	US
Kind code	B2
Filing date	Aug 28, 2020
Priority date	Aug 11, 2020
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.

First claim

What is claimed is:

1. A method of forming a microvia, the method comprising:
depositing a conductive seed layer on a substrate;
depositing a first conductive layer on the conductive seed layer;
patterning the first conductive layer to form first conductive lines or capture pads;
depositing a first dielectric layer;
patterning the first dielectric layer to form at least one via having a diameter;
depositing a conductive material into the at least one via to form at least one conductive pillar with a height;
removing the first dielectric layer and the conductive seed layer from the substrate; and
depositing a second dielectric layer around the at least one conductive pillar.

2. The method of claim 1 , further comprising performing an ashing process after removing the first dielectric layer and the conductive seed layer.

3. The method of claim 1 , further comprising:
depositing the second dielectric layer with a thickness greater than the height of the at least one conductive pillar; and
planarizing the second dielectric layer to expose a top of the at least one conductive pillar.

4. The method of claim 1 , further comprising:
depositing a second conductive layer on the second dielectric layer and the at least one conductive pillar; and
patterning the second conductive layer to form second conductive lines or capture pads.

5. The method of claim 1 , wherein the conductive seed layer and the conductive material comprise copper.

6. The method of claim 1 , wherein the first dielectric layer comprises a photosensitive dielectric and patterning at least one via into the first dielectric layer comprises a photolithography process.

7. The method of claim 6 , wherein the photosensitive dielectric comprises a positive tone photoresist.

8. The method of claim 6 , wherein the photosensitive dielectric comprises a negative tone photoresist.

9. The method of claim 1 , wherein the second dielectric layer comprises an RDL polymer dielectric.

10. The method of claim 9 , wherein the RDL polymer dielectric comprises a silica filled epoxy.

11. The method of claim 1 , wherein the diameter of the at least one via is less than or equal to 20 μm.

12. The method of claim 11 , wherein the diameter of the at least one via is in a range of 1 μm to 20 μm.

13. The method of claim 1 , wherein the at least one via is formed within a tolerance of a predetermined x-y location, the tolerance being less than or equal to 0.5 μm from the predetermined x-y location.

14. The method of claim 1 , wherein the at least one via is formed to be in contact with a conductive line without a capture pad.

15. A method of forming a microvia, the method comprising:
depositing a copper seed layer on a substrate;
depositing a first copper layer on the copper seed layer;
patterning the first copper layer to form a first copper line;
depositing a first dielectric layer on the first copper line, the first dielectric layer being photosensitive;
patterning the first dielectric layer to form a via having a diameter, the via positioned over the first copper line;
depositing a copper material into the via to form a copper pillar;
removing the first dielectric layer and the copper seed layer from the substrate;
depositing a second dielectric layer around and over the copper pillar, the second dielectric layer comprising silica filled epoxy;
planarizing the second dielectric layer to expose a top of the copper pillar;
depositing a second copper layer on the second dielectric layer and the copper pillar; and
patterning the second copper layer to form a second copper line.

16. The method of claim 15 , wherein the diameter of the via is greater than or equal to 1 μm and less than or equal to 20 μm.

17. The method of claim 15 , wherein the via is formed within a tolerance of a predetermined x-y location, the tolerance being less than or equal to 0.5 μm from the predetermined x-y location.

18. The method of claim 15 , wherein at least two copper pillars are formed to connect two first copper lines to a single second copper line or vice versa.

19. A non-transitory computer readable medium including instructions, that, when executed by a controller of a processing system, cause the processing system to perform operations of:
depositing a copper seed layer on a substrate;
depositing a first conductive layer on the copper seed layer;
patterning the first conductive layer to form first conductive lines or capture pads;
depositing a first dielectric layer;
patterning the first dielectric layer to form a via having a diameter;
depositing a copper material into the via to form a copper pillar;
etching the first dielectric layer and the copper seed layer from the substrate; and
depositing a second dielectric layer around the copper pillar.

Assignees

• Applied Materials Inc

Inventors

• Buch Chintan
• Gouk Roman
• Verhaverbeke Steven

Classifications

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/66

  Conductive materials thereof · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W72/011 Primary

  Apparatus therefor · CPC title