Wafer singulation process control

Patent metadata

Field	Value
Publication number	US-11315832-B2
Application number	US-201616067748-A
Country	US
Kind code	B2
Filing date	Dec 23, 2016
Priority date	Dec 30, 2015
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A method for monitoring and controlling a substrate singulation process is described. Device edges are imaged and identified for analysis. Discrepancies in device edges are noted and used to modify a singulation process and to monitor the operation of singulation processes for anomalous behavior.

First claim

What is claimed is:

1. A method of characterizing a singulation process comprising:
identifying a profile of a predetermined portion of a peripheral edge of a first IC device that has been separated from a substrate;
identifying a profile of a predetermined portion of a peripheral edge of a second IC device that has been separated from the substrate, the predetermined portion of the peripheral edge of the second IC device being retained adjacent to the predetermined portion of the peripheral edge of the first IC device during the steps of identifying; and,
comparing the profiles of the predetermined portions of the peripheral edge of the first and second IC devices to identify one of a gap between the profiles and an overlap between the profiles, if any.

2. The method of characterizing a singulation process of claim 1 :
wherein prior to the steps of identifying, the method further comprising separating at least a portion of a contiguous substrate into at least the first IC device and the second IC device such that the first and second IC devices having adjoining edges;
wherein the steps of identifying include:
capturing at least one image of each of the adjoining edges of the first and second IC devices;
establishing a profile of each of the adjoining edges of the first and second IC devices;

wherein the step of comparing includes:
overlaying the profiles of the adjoining edges;
identifying discrepant portions of the adjoining edges from the overlaid profiles of the adjoining edges, if any; and,

the method further comprising modifying the separating step and/or an apparatus for carrying out the separating step to reduce the likelihood that the separating step will result in a discrepant portion of subsequently formed adjoining edges of at least another first IC device and another second IC device.

3. The method of characterizing a singulation process of claim 2 wherein the step of identifying discrepant portions further comprises determining whether a discrepancy between the profiles of the adjoining edges is indicative of one of a chip and a delamination.

4. The method of characterizing a singulation process of claim 3 wherein a chip is determined by identifying a gap between the profiles of the adjoining edges.

5. The method of characterizing a singulation process of claim 3 wherein a delamination is determined by identifying an overlap between the profiles of the adjoining edges.

6. The method of characterizing a singulation process of claim 2 , wherein during the step of separating, the contiguous substrate is secured to a support, and further wherein throughout the steps of identifying, the first and second IC devices remain secured relative to one another by the support.

7. The method of characterizing a singulation process of claim 1 further comprising:
determining a roughness of each of the profiles of the predetermined portions of the peripheral edge of the first and second IC devices;
determining whether the roughness of either of the profiles of the predetermined portions of the peripheral edge of the first and second IC devices exceeds a predetermined threshold that defines an acceptable level of quality; and,
identifying whether the roughness of either of the profiles of the predetermined portions of the peripheral edge of the first and second IC devices differs by more than a predetermined threshold which defines an acceptable level of quality.

8. The method of characterizing a singulation process of claim 1 further comprising:
determining a line of best fit for each of the profiles of the predetermined portions of the peripheral edge of the first and second IC devices; and,
determining whether the lines of best fit for each of the profiles of the predetermined portions of the peripheral edge of the first and second IC devices are out of parallel to one another by more than a predetermined threshold which defines an acceptable level of quality.

9. The method of characterizing a singulation process of claim 8 wherein the line of best fit is selected from a group consisting of linear and curvilinear.

10. The method of characterizing a singulation process of claim 1 further comprising:
identifying a boundary of a patterned area of at least one of the first and second IC devices; and,
determining a relative distance and orientation between the boundary and the profile of the predetermined portion of the peripheral edge of the respective IC device.

11. An integrated circuit device manufactured by the process of claim 1 .

12. The method of characterizing a singulation process of claim 1 , wherein throughout the steps of identifying, the first and second IC devices are secured relative to one another by a support.

13. The method of characterizing a singulation process of claim 2 , wherein the overlaying step includes forming a known relationship between the profiles of each of the adjoining edges of the first and second IC devices.

14. The method of characterizing a singulation process of claim 2 , wherein the overlaying step includes generating a transform that relates a position and orientation of a segment of the profile of the first IC device with a corresponding segment of the profile of the second IC device.

15. The method of characterizing a singulation process of claim 2 , wherein the modifying step includes modifying at least one of a singulation process feed rate, temperature, pressure and alignment.

16. The system of claim 13 further comprising:
means for identifying a boundary of a patterned area of at least one of the first and second IC devices; and
means for determining a relative distance and orientation between the boundary and the profile of the predetermined portion of the peripheral edge of the respective IC device.

17. The system of claim 13 , wherein the means for identifying is configured to operate while the first and second IC devices are secured relative to one another by a support.

18. The system of claim 13 , wherein:
the means for identifying includes:
means for capturing at least one image of each of the adjoining edges of the first and second IC devices, and
means for establishing a profile of each of the adjoining edges of the first and second IC devices; and

the means for comparing includes:
means for overlaying the profiles of the adjoining edges, and
means for identifying discrepant portions of the adjoining edges from the overlaid profiles of the adjoining edges, if any.

Assignees

• Rudolph Tech Inc
• Onto Innovation Inc

Inventors

• Fitzgerald Wayne

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• G06T7/55

  from multiple images · CPC title

• G06T2207/20212

  Image combination · CPC title