Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same

Patent metadata

Field	Value
Publication number	US-11315635-B2
Application number	US-202117152696-A
Country	US
Kind code	B2
Filing date	Jan 19, 2021
Priority date	Sep 30, 2020
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions. The channel region is continuous between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region. A second floating gate is disposed over and insulated from a second portion of the channel region. A first coupling gate is disposed over and insulated from the first floating gate. A second coupling gate is disposed over and insulated from the second floating gate. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. An erase gate is disposed over and insulated from the word line gate.

First claim

What is claimed is:

1. A method of forming a memory cell, comprising:
forming a first insulation layer on a semiconductor substrate having a first conductivity type;
forming a first conductive layer on the first insulation layer;
forming a second insulation layer on the first conductive layer;
forming a second conductive layer on the second insulation layer;
forming a third insulation layer on the second conductive layer;
forming a trench that extends through the third insulation layer, the second conductive layer, and the second insulation layer;
forming insulation spacers along a sidewall of the trench;
extending the trench through the first conductive layer between the insulation spacers;
forming a word line gate in the trench, wherein the word line gate is disposed vertically over and insulated from the substrate;
forming an erase gate in the trench, wherein the erase gate is disposed vertically over and insulated from the word line gate;
removing portions of the second conductive layer while maintaining first and second portions of the second conductive layer as respective first and second coupling gates, and removing portions of the first conductive layer while maintaining first and second portions of the first conductive layer as respective first and second floating gates; and
forming first and second regions in the substrate and having a second conductivity type different than the first conductivity type, wherein the first region is adjacent to the first floating gate and the second region is adjacent to the second floating gate, and wherein a continuous channel region in the substrate extends between the first and second regions;
wherein:
the first floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate,
the second floating gate is disposed over and insulated from the substrate and laterally adjacent to and insulated from the word line gate,
the first coupling gate is disposed over and insulated from the first floating gate, and
the second coupling gate is disposed over and insulated from the second floating gate.

2. The method of claim 1 , wherein:
the word line gate is disposed laterally adjacent to and insulated from the first and second floating gates; and
the erase gate is disposed laterally adjacent to and insulated from the first and second coupling gates.

3. The method of claim 1 , wherein before the forming of the erase gate, the method further comprising:
removing one of the insulation spacers from along the sidewall of the trench.

4. The method of claim 3 , wherein the erase gate includes a first notch facing an edge of the first floating gate and a second notch facing an edge of the second floating gate.

5. The method of claim 1 , wherein the first floating gate is partially disposed over and insulated from the first region, and the second floating gate is partially disposed over and insulated from the second region.

6. The method of claim 1 , wherein insulation between the word line gate and the substrate is thinner than insulation between the first and second floating gates and the substrate.

7. The method of claim 1 , wherein insulation between the erase gate and the first and second floating gates is thinner than insulation between the word line gate and the first and second floating gates.

8. A method of forming a memory cell, comprising:
forming a first insulation layer on a semiconductor substrate having a first conductivity type;
forming a first conductive layer on the first insulation layer;
forming a second insulation layer on the first conductive layer;
forming a second conductive layer on the second insulation layer;
forming a third insulation layer on the second conductive layer;
removing portions of the second conductive layer while maintaining first and second portions of the second conductive layer as respective first and second coupling gates, and removing portions of the first conductive layer while maintaining first and second portions of the first conductive layer as respective first and second floating gates;
forming a word line gate that is disposed vertically over and insulated from the substrate and disposed laterally between the first and second floating gates;
forming an erase gate that is disposed vertically over and insulated from the word line gate and disposed laterally between the first and second coupling gates; and
forming first and second regions in the substrate and having a second conductivity type different than the first conductivity type, wherein the first region is adjacent to the first floating gate and the second region is adjacent to the second floating gate, and wherein a continuous channel region in the substrate extends between the first and second regions;
after the removing of portions of the second conductive layer and before the removing of portions of the first conductive layer, forming insulation spacers along sidewalls of the first coupling gate and along sidewalls of the second coupling gate;
before the forming of the erase gate, removing one of the insulation spacers from along one of the sidewalls of the first coupling gate and along one of the sidewalls of the second coupling gate;
wherein:
the first floating gate is disposed over and insulated from the substrate,
the second floating gate is disposed over and insulated from the substrate,
the first coupling gate is disposed over and insulated from the first floating gate, and
the second coupling gate is disposed over and insulated from the second floating gate.

9. The method of claim 8 , wherein the erase gate includes a first notch facing an edge of the first floating gate and a second notch facing an edge of the second floating gate.

10. The method of claim 8 , wherein:
the word line gate is disposed laterally adjacent to and insulated from the first and second floating gates; and
the erase gate is disposed laterally adjacent to and insulated from the first and second coupling gates.

11. The method of claim 8 , wherein the first floating gate is partially disposed over and insulated from the first region, and the second floating gate is partially disposed over and insulated from the second region.

12. The method of claim 8 , wherein insulation between the word line gate and the substrate is thinner than insulation between the first and second floating gates and the substrate.

13. The method of claim 8 , wherein insulation between the erase gate and the first and second floating gates is thinner than insulation between the word line gate and the first and second floating gates.

Assignees

• Silicon Storage Tech Inc

Inventors

• Wang Chunming
• Liu Xian
• Song guo xiang
• Xing leo
• Do Nhan

Classifications

• H10D30/6892

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• G11C2216/04

  Nonvolatile memory cell provided with a separate control gate for erasing the cells, i.e. erase gate, independent of the normal read control gate · CPC title

• G11C16/0425 Primary

  comprising cells containing a merged floating gate and select transistor · CPC title

• G11C16/0458 Primary

  comprising two or more independent floating gates which store independent data · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title