High density split-gate memory cell

Patent metadata

Field	Value
Publication number	US-10658027-B2
Application number	US-201615002302-A
Country	US
Kind code	B2
Filing date	Jan 20, 2016
Priority date	Jan 22, 2015
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

First claim

What is claimed is:

1. A method of forming a memory device, comprising:
forming a plurality of separated first trenches into a surface of a semiconductor substrate, wherein the first trenches are parallel to each other and extend in a first direction and define active regions of the substrate between the first trenches;
filling the first trenches with insulation material;
forming a first insulation layer on the surface of the substrate in each of the active regions;
forming a first conductive layer on the first insulation layer in each of the active regions;
forming a second insulation layer on the first conductive layer in each of the active regions;
forming a second conductive layer on the second insulation layer in each of the active regions;
forming a third insulation layer on the second conductive layer in each of the active regions;
forming a plurality of separated second trenches through the third insulation layer, wherein the second trenches are parallel to each other and extend in a second direction perpendicular to the first direction;
extending the second trenches through the second conductive layer and the second insulation layer;
extending the second trenches through the first conductive layer, leaving side portions of the first conductive layer exposed and leaving the first insulation layer on the surface of the substrate at the bottom of the second trenches;
forming a fourth insulation layer vertically and directly on the first insulation layer at the bottom of the second trenches and along the exposed portions of the first conductive layer, wherein the fourth insulation layer is not in direct contact with the substrate;
filling the second trenches with conductive material, wherein the conductive material is insulated from the first conductive layer by the fourth insulation layer and from the substrate surface in a vertical direction by the first insulation layer and the fourth insulation layer;
forming a plurality of third trenches through the third insulation layer, wherein the third trenches are parallel to each other and extend in the second direction such that the second and third trenches alternate each other;
extending the third trenches through the second conductive layer, the second insulation layer, and the first conductive layer;
performing an implantation to form drain regions in the substrate under the third trenches.

2. The method of claim 1 , further comprising:
forming spacers of insulation material along sidewalls of the second trenches after the extending of the second trenches through the second conductive layer and the second insulation layer, and before the extending of the second trenches through the first conductive layer.

3. The method of claim 1 , further comprising:
forming spacers of insulation material along sidewalls of the third trenches after the extending of the third trenches through the second conductive layer, the second insulation layer, and the first conductive layer.

4. The method of claim 1 , wherein the first and second conductive layers are polysilicon.

5. The method of claim 1 , wherein the first insulation layer is oxide.

6. The method of claim 1 , wherein the second insulation layer is an ONO insulation layer comprising oxide, nitride, and oxide sublayers.

7. A method of forming a memory device, comprising:
forming a plurality of separated first trenches into a surface of a semiconductor substrate, wherein the first trenches are parallel to each other and extend in a first direction and define active regions of the substrate between the first trenches;
filling the first trenches with insulation material;
forming a first insulation layer on the surface of the substrate in each of the active regions;
forming a first conductive layer on the first insulation layer in each of the active regions;
forming a second insulation layer on the first conductive layer in each of the active regions;
forming a second conductive layer on the second insulation layer in each of the active regions;
forming a third insulation layer on the second conductive layer in each of the active regions;
forming a plurality of separated second trenches through the third insulation layer, wherein the second trenches are parallel to each other and extend in a second direction perpendicular to the first direction;
extending the second trenches through the second conductive layer and the second insulation layer;
extending the second trenches through the first conductive layer, leaving side portions of the first conductive layer exposed and leaving the first insulation layer on the surface of the substrate at the bottom of the second trenches;
forming a fourth insulation layer vertically on the first insulation layer at the bottom of the second trenches and along the exposed portions of the first conductive layer, wherein the fourth insulation layer is not in direct contact with the substrate;
filling the second trenches with conductive material, wherein the conductive material is insulated from the first conductive layer by the fourth insulation layer and from the substrate surface in a vertical direction by the first insulation layer and the fourth insulation layer;
forming a plurality of third trenches through the third insulation layer, wherein the third trenches are parallel to each other and extend in the second direction such that the second and third trenches alternate each other;
extending the third trenches through the second conductive layer, the second insulation layer, and the first conductive layer;
performing an implantation to form drain regions in the substrate under the third trenches;
wherein the extending of the third trenches further includes extending the third trenches through the first insulation layer.

Assignees

• Silicon Storage Tech Inc

Inventors

• Do Nhan
• Liu Xian
• Tiwari Vipin
• Tran Hieu Van

Classifications

• G11C16/0458 Primary

  comprising two or more independent floating gates which store independent data · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• H01L27/11521

  Electricity · mapped topic

• H01L29/40114

  Electricity · mapped topic