Voltage regulator

Patent metadata

Field	Value
Publication number	US-11300985-B2
Application number	US-202017070304-A
Country	US
Kind code	B2
Filing date	Oct 14, 2020
Priority date	Oct 23, 2019
Publication date	Apr 12, 2022
Grant date	Apr 12, 2022

Abstract

A device includes a current source, a first transistor connected between a first supply rail and an output terminal, and a second transistor connected between the output terminal and a first terminal of the current source, wherein a second terminal of the current source is connected to a second supply rail. A variable-gain amplifier circuit responds to a potential at the first terminal of the current source by applying a potential to the control terminal of the first transistor. A gain of the amplifier circuit is determined by a potential at the output terminal.

First claim

The invention claimed is:

1. A device, comprising:
a first current source;
a first transistor connected between a first supply rail and an output terminal;
a second transistor connected between the output terminal and a first terminal of the first current source, wherein a second terminal of the first current source is connected to a second supply rail; and
a variable-gain amplifier circuit configured to apply a first potential to a control terminal of the first transistor in response to a second potential at the first terminal of the first current source, wherein a gain of the variable-gain amplifier circuit is determined by a third potential at the output terminal.

2. The device of claim 1 , wherein the variable-gain amplifier circuit comprises:
a third transistor connected between the first terminal of the first current source and the control terminal of the first transistor; and
a second current source connected between the first supply rail and the control terminal of the first transistor, the second current source being configured to deliver a variable current having a value depending on the third potential at the output terminal.

3. The device of claim 2 , wherein a control terminal of the third transistor is connected to a node of application of a bias potential.

4. The device of claim 2 , further comprising a first circuit configured to apply a control signal to the second current source, wherein the control signal applied to the second current source is based on the third potential at the output terminal.

5. The device of claim 4 , wherein the first circuit comprises:
a fourth transistor connected in a current mirror configuration with a fifth transistor;
a sixth transistor connected to the output terminal and in series with the fifth transistor, wherein a control terminal of the sixth transistor is connected to a control terminal of the second transistor; and
a seventh transistor series-connected with the fourth transistor between the first supply rail and the second supply rail.

6. The device of claim 5 , wherein the second current source comprises an eighth transistor connected in a current mirror configuration with the seventh transistor.

7. The device of claim 1 , further comprising a second circuit configured to apply a control signal to the second transistor.

8. The device of claim 7 , wherein the second circuit is configured to determine the control signal applied to the second transistor based on a set point value for the third potential at the output terminal.

9. The device of claim 8 , wherein the second circuit comprises:
an operational amplifier having a first input configured to receive a reference potential representative of said set point value; and
a ninth transistor having a first conduction terminal coupled to the second supply rail via a third current source, wherein the ninth transistor has a second conduction terminal connected to a second input of the operational amplifier, and has a control terminal configured to apply the control signal to the second transistor.

10. The device of claim 9 , wherein the second circuit further comprises:
a tenth transistor having a first conduction terminal connected to the second conduction terminal of the ninth transistor, a second conduction terminal connected to the first supply rail and a control terminal connected to an output of the operational amplifier.

11. The device of claim 10 , wherein the control terminal of the ninth transistor and the first conduction terminal of the ninth transistor are interconnected, and wherein the first input of the operational amplifier is an inverting input.

12. The device of claim 9 , wherein the second circuit further comprises:
a fourth current source connected between the second conduction terminal of the ninth transistor and the first supply rail; and
a tenth transistor and a resistive element series-connected between the first conduction terminal of the ninth transistor and the first supply rail, wherein a control terminal of the tenth transistor is configured to receive a bias potential that is also applied to a control terminal of a third transistor, and wherein a conduction terminal of the tenth transistor is connected to the first conduction terminal of the ninth transistor.

13. The device of claim 12 , wherein the resistive element comprises a diode-connected transistor.

14. The device of claim 9 , wherein the second circuit is configured to impose a same potential on the first terminal of the first current source and on the first conduction terminal of the ninth transistor.

15. The device of claim 1 , forming a voltage regulator.

16. The device of claim 1 , implemented by a single integrated circuit.

17. The device of claim 16 , wherein the device comprises no capacitor connected between the output terminal and the second supply rail.

18. The device of claim 1 , further comprising a conductive path coupling the output terminal to an input terminal of the variable-gain amplifier circuit, wherein the conductive path is separate from the second supply rail.

19. A device, comprising:
a first transistor having a first current conduction path connected between a first supply rail and an output terminal;
a second transistor having a second current conduction path connected between the output terminal and a first intermediate node;
a first current source having a third current conduction path connected between the first intermediate node and a second supply rail;
a second current source having a fourth current conduction path connected between the first supply rail and a control terminal of the first transistor;
a third transistor having a fifth current conduction path connected between the control terminal of the first transistor and the first intermediate node; and
a sixth current conduction path connected between the output terminal and a control terminal of the second current source controlling a magnitude of current being output from the second current source.

20. The device of claim 19 , wherein a control terminal of the third transistor is biased by a bias voltage.

21. The device of claim 19 , further comprising a circuit configured to control the second current source in response to a voltage at the output terminal.

22. The device of claim 19 , wherein the second transistor has a control terminal configured to receive a control signal and further comprising a circuit configured to generate the control signal in response to a reference voltage.

Assignees

• St Microelectronics Rousset

Inventors

• Fort Jimmy

Classifications

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• G05F3/262 Primary

  using field-effect transistors only · CPC title

• G05F1/461

  using an operational amplifier as final control device · CPC title

• G05F1/445 Primary

  being transistors in series with the load · CPC title