Current-feedback operational amplifier

Patent metadata

Field	Value
Publication number	US-2015077183-A1
Application number	US-201314031806-A
Country	US
Kind code	A1
Filing date	Sep 19, 2013
Priority date	Sep 19, 2013
Publication date	Mar 19, 2015
Grant date	—

Abstract

An integrated, fully-differential current-feedback transimpedance operational amplifier circuit is disclosed. The circuit can be configured as a class-AB, low-impedance input stage, followed by an inverter-based, rail-to-rail output stage. For enhancing the open-loop transimpedance gain of the amplifier without consuming additional DC power, the same bias current is used both in the input stage and in a gain-enhancement stage serving as its load. The gain-enhancement stage can be either DC- or AC-coupled to the input of the amplifier. In the case of DC coupling, an output common-mode feedback loop can be used to provide the proper operating voltages in the amplifier.

First claim

What is claimed is:

1 . An apparatus comprising an operational amplifier, the operational amplifier comprising:
an input stage configured to receive a differential input current at an input port and to generate a first voltage signal, the differential current corresponding to a difference between a first input current at a non-inverting input node and a second input current at an inverting input node, the input stage comprising a first input transistor, a second input transistor, a third input transistor, and a fourth input transistor; and a gain-enhancement stage comprising a first gain-enhancement transistor, a second gain-enhancement transistor, a third gain-enhancement transistor, and a fourth gain-enhancement transistor; the first and third input transistors and the third and fourth gain-enhancement transistors comprising a first semiconductor type, and the second and fourth input transistors and the first and second gain-enhancement comprising a second semiconductor type complementary to the first semiconductor type; wherein a source of the first input transistor, a source of the second input transistor, a gate of the second gain-enhancement transistor, and a gate of the fourth gain-enhancement transistor are operatively coupled to the non-inverting input node, and wherein a source of the third input transistor, a source of the fourth input transistor, a gate of the first gain-enhancement transistor, and a gate of the third gain-enhancement transistor are operatively coupled to the inverting input node, such that the gates of the gain-enhancement transistors are cross-coupled to the input port to provide a second voltage signal in phase with the first voltage signal.

2 . The apparatus of claim 1 , wherein a gate of the first input transistor and a gate of the third input transistor are operatively coupled to a first input stage bias voltage, and wherein a gate of the second input transistor and a gate of the fourth input transistor are operatively coupled to a second input stage bias voltage.

3 . The apparatus of claim 2 , further comprising:
a first tail transistor and a second tail transistor; a common-mode control circuit comprising a first control circuit and a second control circuit wherein the first control circuit is configured to provide a voltage to a gate of the first tail transistor and the second control circuit is configured to provide a voltage to a gate of the second tail transistor, and wherein through local common-mode negative feedback, the common-mode control circuit is configured to control the first and second tail transistors for biasing DC operating currents of the input stage; and an output stage configured to provide a differential voltage at an output port, the differential voltage corresponding to a difference between a first output voltage at an inverting output node and a second output voltage at a non-inverting output node, the output stage comprising a first output transistor, a second output transistor, a third output transistor, and a fourth output transistor; the first and third output transistors comprising the first transistor type, and the second and fourth output transistors comprising the second, complementary transistor type.

4 . The apparatus of claim 3 , wherein a gate of the first output transistor is operatively coupled to a first input of the first control circuit, a drain of the first gain-enhancement transistor, and a drain of the first input transistor, wherein a gate of the second output transistor is operatively coupled to a first input of the second control circuit, a drain of the third gain-enhancement transistor, and a drain of the second input transistor, and wherein a drain of the first output transistor and a drain of the second output transistor are operatively coupled to the first output node.

5 . The apparatus of claim 4 , wherein a gate of the third output transistor is operatively coupled to a second input of the first control circuit, a drain of the second gain-enhancement transistor, and a drain of the third input transistor, wherein a gate of the fourth output transistor is operatively coupled to a second input of the second control circuit, a drain of the fourth gain-enhancement transistor, and a drain of the fourth input transistor, and wherein a drain of the third output transistor and a drain of the fourth output transistor are operatively coupled to the second output node.

6 . The apparatus of claim 5 , wherein the first control circuit comprises a first pair of common-mode resistors arranged in series comprising a first end configured to provide the first input, a second end configured to provide the second input, and a common-node configured to provide the output of the first control circuit, and wherein the second control circuit comprises a second pair of common-mode resistors arranged in series comprising a first end configured to provide the first input, a second end configured to provide the second input, and a common-node configured to provide the output of the second control circuit.

7 . The apparatus of claim 6 , wherein DC drain currents of the first and second output transistors are approximately equal to DC drain currents of the first and second input transistors, and wherein DC drain currents of the third and fourth output transistors are approximately equal to DC drain currents of the third and fourth input transistors.

8 . The apparatus of claim 6 , wherein the first control circuit further comprises a third common-mode resistor, a first current source, and a second current source, wherein a first node of the first current source is coupled to the gate of a first tail transistor and a first end of the third common-mode resistor, wherein a second end of the third common-mode resistor is coupled to the common-node of the first pair of common-mode resistors and a first node of the second current source; and
wherein the second control circuit further comprises a fourth common-mode resistor, a third current source, and a fourth current source, wherein a first node of the third current source is coupled to the gate of a second tail transistor and a first end of the fourth common-mode resistor, and wherein a second end of the fourth common-mode resistor is coupled to the common-node of the second pair of common-mode resistors and a first node of the fourth current source; and wherein currents flowing through the third and the fourth common-mode resistors level-shift voltages at common-mode control circuit inputs to vary drain-source headroom of input stage transistors and gain-enhancement stage transistors.

9 . The apparatus of claim 6 , wherein the common-mode control circuit further comprises a third control circuit comprising an operational transconductance amplifier and a third pair of common-mode resistors arranged in series comprising a common-node, wherein the third pair of common-mode resistors are operatively coupled to a non-inverting input of the operational transconductance amplifier via the common-node, a first end of the third pair operatively coupled to the inverting output node, and a second end of the third pair operatively coupled to the non-inverting output node;
wherein an inverting input of the operational transconductance amplifier is provided with a common-mode reference voltage, and an output of the operational transconductance amplifier is coupled to the drain of the second tail transistor; and wherein the operational transconductance amplifier is configured to generate an output DC current that is superimposed on a DC drain current of the second tail transistor and closes a negative feedback loop through the gain-enhancement stage and the output stage.

10 . The apparatus of claim 6 , wherein th

Assignees

• Analog Devices Inc

Inventors

• Ciubotaru Alexandru A

Classifications

• H03F3/45179 Primary

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F2003/45008

  Electricity · mapped topic

• H03F2203/45406

  the CMCL comprising a common source node of a long tail FET pair as an addition circuit · CPC title

• H03G3/00

  Gain control in amplifiers or frequency changers · CPC title

• H03F2203/45431

  the CMCL output control signal being a current signal · CPC title