Thin film transistors with spacer controlled gate length

Patent metadata

Field	Value
Publication number	US-11296087-B2
Application number	US-201716473592-A
Country	US
Kind code	B2
Filing date	Mar 31, 2017
Priority date	Mar 31, 2017
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
a first thin film transistor (TFT) that includes:
a first gate electrode within a gate dielectric layer above a substrate;
a channel layer above the first gate electrode;
a first source electrode, a first drain electrode, and a first spacer, wherein the first source electrode, the first drain electrode, and the first spacer are above the channel layer, the first drain electrode is separated from the first source electrode by the first spacer, the first spacer overlaps with the first gate electrode, wherein a width of the first spacer between the first source electrode and the first drain electrode is substantially equal to a width of the first gate electrode, the first source electrode has a first width, and the drain electrode has a second width different from the first width;

a second TFT coupled to the first TFT, the second TFT includes:
a second gate electrode within the gate dielectric layer above the substrate, the channel layer above the second gate electrode;
a second source electrode, a second drain electrode, and a second spacer,

wherein the second source electrode, the second drain electrode, and the second spacer are above the channel layer, wherein the second source electrode is separated from the first source electrode by a pitch along a horizontal plane;
the second spacer positioned between the first drain electrode and the second source electrode and overlapping the second gate electrode; and
an isolation gate within the gate dielectric layer between the first gate electrode and the second gate electrode, wherein a third spacer between the first drain electrode and the second source electrode overlaps with the isolation gate.

2. The IC of claim 1 , wherein the second spacer has a width that is about 5% to 15% of a width of the second gate electrode.

3. The IC of claim 1 , wherein the first source electrode includes a first conductive material, and the first drain electrode includes a second conductive material different from the first conductive material.

4. The IC of claim 1 , further comprising:
a top dielectric layer above the first source electrode, the first drain electrode, and the first spacer, wherein the first spacer includes a first dielectric material, and the top dielectric layer includes a second dielectric material different from the first dielectric material.

5. The IC of claim 1 , further comprising:
a gate dielectric layer above the gate electrode and below the channel layer, wherein the gate dielectric layer includes silicon and oxygen, silicon and nitrogen, yttrium and oxygen, silicon, oxygen, and nitrogen, aluminum and oxygen, hafnium and oxygen, tantalum and oxygen, or titanium and oxygen.

6. The IC of claim 1 , wherein the channel layer includes amorphous silicon, zinc (Zn), or oxygen (O).

7. The IC of claim 1 , wherein the TFT is above an interconnect, and the interconnect is above the substrate.

8. A computing device, comprising:
a circuit board; and
a memory device coupled to the circuit board and including a memory array, wherein the memory array includes a plurality of memory cells, a memory cell of the plurality of memory cells includes an integrated circuit (IC) and a storage cell, and wherein the IC includes:
a first thin film transistor (TFT) that includes:
a first gate electrode coupled to a first word line of the memory array;
a channel layer above the first gate electrode;
a first source electrode, a first drain electrode, and a first spacer, wherein the first source electrode, the first drain electrode, and the first spacer are above the channel layer, the first source electrode is coupled to a first source line of the memory array, the first drain electrode is coupled to the storage cell, the first drain electrode is separated from the first source electrode by the first spacer, the first spacer overlaps with the first gate electrode, wherein a width of the first spacer between the first source electrode and the first drain electrode is greater than or equal to a width of die first gate electrode, the first source electrode has a first width, and the first drain electrode has a second width different from the first width;

a second TFT coupled to the first TFT, the second TFT includes:
a second gate electrode coupled to a second word line of the memory array;
a second source electrode, a second drain electrode, and a second spacer,

wherein the second source electrode, the second drain electrode, and the second spacer are above the channel layer, wherein the second source electrode is separated from the first source electrode by a pitch along a horizontal plane;
the second spacer positioned between the first drain electrode and the second source electrode; and
an isolation gate within a gate dielectric layer between the first gate electrode and the second gate electrode, wherein a third spacer between the first drain electrode and the second source electrode overlaps with the isolation gate; and
wherein the storage cell is coupled to a bit line of the memory array.

9. The computing device of claim 8 , wherein the second first spacer has a width that is about 5% to 15% of a width of the second sate electrode.

10. The computing device of claim 8 , wherein the first source electrode includes a first conductive material, and the first drain electrode includes a second conductive material different from the first conductive material.

11. The computing device of claim 8 , wherein the TFT further includes:
a top dielectric layer above the first source electrode, the first drain electrode, and the first spacer, wherein the first spacer includes a first dielectric material, and the top dielectric layer includes a second dielectric material different from the first dielectric material.

12. The computing device of claim 8 , wherein the IC further includes:
a gate dielectric layer above the first gate electrode and below the channel layer; wherein the gate dielectric layer includes silicon and oxygen, silicon and nitrogen, yttrium and oxygen, silicon, oxygen, and nitrogen, aluminum and oxygen, hafnium and oxygen, tantalum and oxygen, or titanium and oxygen.

13. The computing device of claim 8 , wherein the channel layer includes amorphous silicon, zinc (Zn), or oxygen (O).

14. The computing device of claim 8 , wherein the IC is above an interconnect, and the interconnect is above a substrate.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek A
• Le Van H
• Dewey Gilbert
• Shivaraman Shriram
• Wang Yih
• Ghani Tahir
• Kavalieros Jack T

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D30/6756

  Amorphous oxide semiconductors · CPC title