Methods of forming metal gates

US11295990B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11295990-B2
Application numberUS-202016735184-A
CountryUS
Kind codeB2
Filing dateJan 6, 2020
Priority dateApr 30, 2018
Publication dateApr 5, 2022
Grant dateApr 5, 2022

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  1. Title

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  2. Abstract

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor structure, comprising: a first fin and a second fin disposed over a substrate; and a first gate structure disposed over the first fin and a second gate structure disposed over the second fin, wherein: the first gate structure includes an interfacial layer over the first fin, a first high-k dielectric layer over the interfacial layer, a phosphate-containing monolayer over the first high-k dielectric layer, a second high-k dielectric layer over the phosphate-containing monolayer, a first work function metal layer over the second high-k dielectric layer, and a bulk conductive layer over the first work function metal layer, and the second gate structure includes the interfacial layer over the second fin, the second high-k dielectric layer over the interfacial layer, a second work function metal layer over the second high-k dielectric layer, and the bulk conductive layer over the second work function metal layer. 2. The semiconductor structure of claim 1 , wherein the first high-k dielectric layer includes lanthanum oxide. 3. The semiconductor structure of claim 2 , wherein the second high-k dielectric layer includes hafnium oxide. 4. The semiconductor structure of claim 3 , wherein the phosphate-containing monolayer is chemically tethered to lanthanum ions included in the first high-k dielectric layer and to hafnium ions included in the second high-k dielectric layer. 5. The semiconductor structure of claim 1 , wherein the first work function metal layer and the second work function metal layer are of different semiconductor types. 6. The semiconductor structure of claim 1 , wherein the first gate structure further includes a third work function metal layer disposed over the first work function metal layer, and wherein the third work function metal layer is similar to the second work function metal layer. 7. The semiconductor structure of claim 1 , wherein each of the first gate structure and the second gate structure further includes a barrier layer over the second high-k dielectric layer. 8. A semiconductor structure, comprising: a first fin and a second fin disposed over a semiconductor substrate; and a high-k metal gate structure having a first portion disposed over the first fin and a second portion disposed over the second fin, wherein the first portion includes a first gate dielectric layer disposed over an interfacial layer, a phosphorous-containing layer disposed over the first gate dielectric layer, a second gate dielectric layer disposed over the phosphorous-containing layer, the second gate dielectric layer being different from the first gate dielectric layer, and a first metal electrode disposed over the second gate dielectric layer, and wherein the second portion includes the interfacial layer, the second gate dielectric layer contacting the interfacial layer, and a second metal electrode contacting the second gate dielectric layer. 9. The semiconductor structure of claim 8 , wherein the phosphorous-containing layer includes oxygen moieties. 10. The semiconductor structure of claim 9 , wherein the first gate dielectric layer includes lanthanum ions, and wherein the lanthanum ions form coordinated bonds with some of the oxygen moieties of the phosphorous-containing layer. 11. The semiconductor structure of claim 9 , wherein the second gate dielectric layer includes hafnium ions, and wherein the hafnium ions form coordinated bonds with some of the oxygen moieties of the phosphorous-containing layer. 12. The semiconductor structure of claim 8 , wherein the first metal electrode includes a first work function metal layer disposed over the first gate dielectric layer, wherein the second metal electrode includes a second work function metal layer disposed over the second gate dielectric layer, and wherein the second work function metal layer is of a different semiconductor type from the first work function metal layer. 13. The semiconductor structure of claim 8 , wherein the first metal electrode includes a first work function metal layer disposed over the first gate dielectric layer and a second work function metal layer disposed over the first work function metal layer, wherein the second metal electrode includes a third work function metal layer disposed over the second gate dielectric layer, wherein the first and the second work function metal layers are of different semiconductor types, and wherein the second and the third work function metal layers are of the same semiconductor type. 14. A semiconductor structure, comprising: a metal gate structure (HKMG) disposed over a first fin and a second fin, the first fin and the second fin protruding from a semiconductor substrate, wherein the metal gate structure includes: a first dielectric layer disposed over the first fin but not over the second fin; a phosphate-containing layer disposed on the first dielectric layer; a second dielectric layer disposed over the first fin and the second fin, wherein the second dielectric layer contacts the phosphate-containing layer, and wherein the second dielectric layer is different from the first dielectric layer in composition; and a bulk conductive layer disposed over the second dielectric layer. 15. The semiconductor structure of claim 14 , wherein the first dielectric layer includes lanthanum ions, and wherein the second dielectric layer includes hafnium ions. 16. The semiconductor structure of claim 15 , wherein the lanthanum ions of the first dielectric layer chemically bond to phosphate ligands at a first surface of the phosphate-containing layer, and wherein the hafnium ions of the second dielectric layer chemically bond to phosphate ligands at a second surface of the phosphate-containing layer opposite to the first surface. 17. The semiconductor structure of claim 14 , further comprising an interfacial layer disposed between the first dielectric layer and the first fin and between the second dielectric layer and the second fin. 18. The semiconductor structure of claim 14 , further comprising a first work function metal layer disposed between the bulk conductive layer and a first portion of the second dielectric layer over the first fin, and a second work function metal layer disposed between the bulk conductive layer and a second portion of the second dielectric layer over the second fin, wherein the first work function metal layer differs from the second work function meta layer in semiconductor type. 19. The semiconductor structure of claim 14 , further comprising a work function metal layer disposed between the second dielectric layer and the bulk conductive layer. 20. The semiconductor structure of claim 14 , wherein a portion of the HKMG disposed over the first fin has a lower threshold voltage that a portion of the HKMG disposed over the second fin.

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Classifications

  • by chemical means · CPC title

  • the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

  • the material containing hafnium, e.g. HfO2 · CPC title

  • with sacrificial oxide · CPC title

  • the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

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What does patent US11295990B2 cover?
A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k d…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/69392. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 05 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).