Display driving device and display device including the same

Patent metadata

Field	Value
Publication number	US-11295650-B2
Application number	US-202016925302-A
Country	US
Kind code	B2
Filing date	Jul 9, 2020
Priority date	Dec 24, 2019
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

The present disclosure discloses a display driving device and a display device including the same, which enable the influence of high voltage noise to be avoided in display panel driving. The display device includes a timing controller configured to transmit a communication signal, which includes a blank pattern and line data, at a horizontal line interval, and a source driver configured to restore the blank pattern and the line data in the communication signal and drive a display panel using the blank pattern and the line data. The timing controller may include a configuration packet in the blank pattern and position the configuration packet in an end period of the blank pattern.

First claim

What is claimed is:

1. A display device comprising:
a timing controller configured to transmit a communication signal, which includes a blank pattern and line data, at a horizontal line interval; and
a source driver configured to restore the blank pattern and the line data in the communication signal and drive a display panel using the blank pattern and the line data,
wherein the timing controller includes a configuration packet in the blank pattern and positions the configuration packet in an end period of the blank pattern, and
the source driver receives a source output enable signal enabled at the horizontal line interval and restores a link through clock training after the source output signal is enabled.

2. The display device of claim 1 , wherein the timing controller positions the configuration packet in the end period of the blank pattern positioned farthest from line data of a previous horizontal line.

3. The display device of claim 1 , wherein when a failure occurs in a link lock signal, the timing controller includes the configuration packet in the blank pattern after the link lock signal is restored.

4. The display device of claim 1 , wherein the source driver provides a link lock signal indicating a lock failure to the timing controller when the lock failure occurs after the source output enable signal is enabled.

5. The display device of claim 4 , wherein the source driver restores the link through at least one of clock training and link training.

6. The display device of claim 5 , wherein the timing controller includes the configuration packet in the blank pattern after the link is restored.

7. The display device of claim 1 , wherein the source driver restores at least one of a control data packet, image data, and a data checksum of the line data in response to a scramble reset signal of the configuration packet.

8. A display driving device comprising at least one source driver configured to restore a blank pattern and line data in a communication signal transmitted at a horizontal line interval and drive a display panel using the blank pattern and the line data,
wherein a configuration packet is included in the blank pattern, and the configuration packet is set to be positioned in an end period of the blank pattern, and
the source driver receives a source output enable signal enabled at the horizontal line interval and restores a link through clock training after the source output enable signal is enable.

9. The display driving device of claim 8 , wherein the configuration packet is set to be positioned in the end period of the blank pattern positioned farthest from line data of a previous horizontal line.

10. The display driving device of claim 8 , wherein when a failure occurs in a link lock signal, the configuration packet is set to be included in the blank pattern after the link lock signal is restored.

11. The display driving device of claim 8 , wherein the source driver provides a link lock signal indicating a lock failure to a timing controller when the lock failure occurs after the source output enable signal is enabled.

12. The display driving device of claim 11 , wherein the source driver restores a link through at least one of clock training and link training.

13. The display driving device of claim 12 , wherein the source driver provides the link lock signal indicating that the link is restored to the timing controller, and receives the configuration packet positioned in an end period of the blank pattern.

14. The display driving device of claim 8 , wherein the source driver restores at least one of a control data packet, image data, and a data checksum of the line data in response to a scramble reset signal of the configuration packet.

Assignees

• Silicon Works Co Ltd

Inventors

• Kim Myung Yu
• Kim Do Seok
• Cho Hyun Pyo
• Moon Yong Hwan

Classifications

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G2310/0264

  Details of driving circuits · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/06

  Details of flat display driving waveforms · CPC title

• G09G2370/10

  Use of a protocol of communication by packets in interfaces along the display data pipeline · CPC title