Data driver performing clock training, display device including the data driver, and method of operating the display device

Patent metadata

Field	Value
Publication number	US-2020184877-A1
Application number	US-201916705114-A
Country	US
Kind code	A1
Filing date	Dec 5, 2019
Priority date	Dec 7, 2018
Publication date	Jun 11, 2020
Grant date	—

Abstract

A display device includes a controller to generate a start frame control signal having a first level in an active period and a second level in a blank period, a load signal toggling between the first level and the second level in the active period and having the second level in the blank period, and a data signal including image data in the active period and a training pattern in the blank period, and a data driver to recover the image data from the data signal based on an internal clock signal to provide display pixels with data voltages in the active period, and to perform a training operation for the internal clock signal using the training pattern in the data signal when both of the start frame control signal and the load signal are maintained as the second level for more than a reference time in the blank period.

First claim

What is claimed is:

1 . A display device comprising:
a display panel comprising a plurality of pixels; a controller configured to generate a start frame control signal that has a first level in an active period and has a second level in a blank period, a load signal that toggles between the first level and the second level in the active period and has the second level in the blank period, and a data signal that comprises image data in the active period and comprises a training pattern in the blank period; and a data driver configured to recover the image data from the data signal based on an internal clock signal to provide the plurality of pixels with data voltages corresponding to the recovered image data in the active period, and to perform a training operation for the internal clock signal using the training pattern comprised in the data signal when both of the start frame control signal and the load signal are maintained as the second level for more than a reference time in the blank period.

2 . The display device of claim 1 , wherein the reference time corresponds to a reference number of training pulses comprised in the training pattern.

3 . The display device of claim 1 , wherein the data driver comprises:
a glitch removal circuit configured to generate a lock enable signal when both of the start frame control signal and the load signal are maintained as the second level for more than the reference time; a clock data recovery circuit configured to recover the image data from the data signal by sampling the image data comprised in the data signal in response to the internal clock signal in the active period, and to perform the training operation for the internal clock signal in response to the lock enable signal in the blank period; and a data converting circuit configured to convert the recovered image data into the data voltages, and to provide the data voltages to the plurality of pixels in the active period.

4 . The display device of claim 3 , wherein the glitch removal circuit comprises:
a level determination circuit configured to generate an enable signal having the first level when both of the start frame control signal and the load signal have the second level; and a maintenance determination circuit configured to generate the lock enable signal having the first level when the enable signal is maintained as the first level for more than the reference time.

5 . The display device of claim 4 , wherein the level determination circuit comprises:
a Schmitt trigger circuit configured to determine a level of the start frame control signal; and a NOR gate configured to perform a NOR operation on an output signal of the Schmitt trigger circuit and the load signal.

6 . The display device of claim 4 , wherein the maintenance determination circuit comprises:
a plurality of serially connected flip-flops configured to sequentially output the enable signal, each of the plurality of serially connected flip-flops having a clock terminal to receive the data signal; and at least one AND gate configured to perform an AND operation on output signals of the plurality of serially connected flip-flops.

7 . The display device of claim 6 , wherein each of the plurality of serially connected flip-flops is configured to store and output an input signal at an edge of each training pulse of the training pattern comprised in the data signal.

8 . The display device of claim 6 , wherein the reference time is determined by a number of the plurality of serially connected flip-flops.

9 . A data driver comprised in a display device, the data driver comprising:
a glitch removal circuit configured to receive, from a controller comprised in the display device, a start frame control signal that has a first level in an active period and has a second level in a blank period, and a load signal that toggles between the first level and the second level in the active period and has the second level in the blank period, and to generate a lock enable signal when both of the start frame control signal and the load signal are maintained as the second level for more than a reference time; a clock data recovery circuit configured to receive, from the controller, a data signal that comprises image data in the active period and comprises a training pattern in the blank period, to recover the image data from the data signal by sampling the image data comprised in the data signal in response to an internal clock signal in the active period, and to perform a training operation for the internal clock signal using the training pattern in response to the lock enable signal in the blank period; and a data converting circuit configured to convert the recovered image data into data voltages, and to provide the data voltages to a plurality of pixels comprised in the display device in the active period.

10 . The data driver of claim 9 , wherein the reference time corresponds to a reference number of training pulses comprised in the training pattern.

11 . The data driver of claim 9 , wherein the glitch removal circuit comprises:
a level determination circuit configured to generate an enable signal having the first level when both of the start frame control signal and the load signal have the second level; and a maintenance determination circuit configured to generate the lock enable signal having the first level when the enable signal is maintained as the first level for more than the reference time.

12 . The data driver of claim 11 , wherein the level determination circuit comprises:
a Schmitt trigger circuit configured to determine a level of the start frame control signal; and a NOR gate configured to perform a NOR operation on an output signal of the Schmitt trigger circuit and the load signal.

13 . The data driver of claim 11 , wherein the maintenance determination circuit comprises:
a plurality of serially connected flip-flops configured to sequentially output the enable signal, each of the plurality of serially connected flip-flops having a clock terminal to receive the data signal; and at least one AND gate configured to perform an AND operation on output signals of the plurality of serially connected flip-flops.

14 . The data driver of claim 13 , wherein each of the plurality of serially connected flip-flops is configured to store and output an input signal at an edge of each training pulse of the training pattern comprised in the data signal.

15 . The data driver of claim 13 , wherein the reference time is determined by a number of the plurality of serially connected flip-flops.

16 . A method of operating a display device, the method comprising:
determining whether both of a start frame control signal and a load signal are maintained as a low level for more than a reference time; performing a training operation for an internal clock signal using a training pattern comprised in a data signal when both of the start frame control signal and the load signal are maintained as the low level for more than the reference time; recovering image data from the data signal based on the internal clock signal; and displaying an image by providing a plurality of pixels comprised in the display device with data voltages corresponding to the recovered image data.

17 . The method of claim 16 , wherein the reference time corresponds to a reference number of training pulses comprised in the training pattern.

18 . The method of claim 16 , wherein determining whether both of the start frame control signal and the load signal are maintained as the low level

Assignees

• Samsung Display Co Ltd

Inventors

• Pyun Kihyun
• Kim Yunmi
• Choi Ji Woong

Classifications

• G09G3/3685 Primary

  Details of drivers for data electrodes · CPC title

• G09G2230/00

  Details of flat display driving waveforms · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title