Apparatuses and methods involving switching between dual inputs of power amplification circuitry

Patent metadata

Field	Value
Publication number	US-11294412-B2
Application number	US-202017091401-A
Country	US
Kind code	B2
Filing date	Nov 6, 2020
Priority date	Dec 4, 2019
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

An example apparatus includes power amplification circuitry and current-level switch circuitry. The power amplification circuitry has a first input port, a second input port, and field-effect transistor (FET) circuitry, the FET circuitry to operate in a saturation mode while drawing power provided at the first input port from a first power source. The current-level switch circuitry is to sense a change in a current-level used to maintain the FET circuitry in the saturation mode and, in response to the sensed change in the current-level, to cause the power amplification circuitry to draw power provided at the second input port from a second power source while maintaining the saturation mode of the FET circuitry.

First claim

The invention claimed is:

1. A dual input, low drop-out voltage regulator for providing a regulated voltage at an output port, the voltage regulator comprising:
power amplification circuitry having a first input port coupled to a first power source and a first power stage coupled to the first input port, a second input port coupled to a second power source and a second power stage coupled to the second input port, wherein an output of the first power stage and an output of the second power stage are coupled to the output port, wherein the first power stage has at least a first intermediate power stage and a first power field-effect transistor (FET), and the second power stage has at least a second intermediate power stage and a second power FET, wherein at least the first power stage and the second power stage form FET circuitry to operate in a saturation mode while drawing power provided at the first input port from a first power source; and
current-level switch circuitry to sense a change in a current-level used to maintain the FET circuitry in the saturation mode, wherein the sensed change in the current level is indicative of the first power FET being out of saturation or at a threshold of being out of saturation, wherein in response to the sensed change in the current-level, the FET circuitry maintains the saturation mode by switching from the first power stage coupled to the first input port to the second power stage coupled to the second input port, and further by, in response to the switch, the second power stage drawing power provided at the second input port from a second power source and the second power FET transitioning to saturation, the FET circuitry maintaining the saturation mode.

2. The voltage regulator of claim 1 , wherein when the FET circuitry operates in the saturation mode when a decrease in an input source voltage to the FET circuitry does not cause a change in the regulated output voltage of the power amplification circuitry.

3. The voltage regulator of claim 1 , wherein the first intermediate stage provides gate control to the first power FET and the second intermediate stage provides gate control to the second power FET, and wherein the first and the second intermediate stages are each adapted to be controlled by a first signal input coupled to an output of the control logic circuitry and the error correction signal output from the error amplifier.

4. The voltage regulator of claim 1 , further including a secure memory element including a circuit to store sensitive data, the secure memory element to operate based on a supply voltage connected to, and with integrity of the stored sensitive data being reliant on, a regulated output voltage provided at the output port, the regulated output voltage to track with the saturation mode of the FET circuitry being maintained.

5. The voltage regulator of claim 1 , wherein during operation, in response to the current-level switch circuitry indicating the sensed change in the current-level, the power amplification circuitry switches on-the-fly from drawing power from the first input port to drawing power from the second input port.

6. The voltage regulator of claim 1 , wherein during operation, in response to the current-level switch circuitry indicating the sensed change in the current-level, the power amplification circuitry is to switch from drawing power from the first input port to drawing power from the second input port, to minimize transient impact on the regulated output voltage level.

7. The voltage regulator of claim 1 , further including a near-field communications circuit to operate based on a regulated output voltage provided in response to an output from the power amplification circuitry, and wherein during operation, in response to the current-level switch circuitry indicating the sensed change in the current-level, the power amplification circuitry is to switch on-the-fly from drawing power from the first input port to drawing power from a battery via the second input port without interfering in communications involving the near-field communications circuit.

8. The voltage regulator of claim 1 , further comprising a feedback path to provide an error-correction signal and
an error amplifier to provide the error-correction signal to the first power stage and the second power stage based on the output from the first and second power stages and a reference voltage, and wherein, during operation, the feedback path is used irrespective of whether the power amplification circuitry draws power from the first input port or the second input port.

9. The voltage regulator of claim 1 , further including a feedback path to provide a feedback signal along a direction from the regulated output voltage signal to another input port of the power amplifier circuitry and wherein, during operation, the feedback path is used irrespective of whether the power amplifier circuitry draws power from the first input port or the second input port.

10. The voltage regulator of claim 1 , further including control logic circuitry and a mode register, the control logic circuitry to configure the mode register with data to select whether during operation, the power amplifier circuitry draws power from the first input port or from the second input port.

11. The voltage regulator of claim 1 , further including a capacitor connected to the output port, wherein the capacitor is to lessen magnitude of power spikes at the output port.

12. The voltage regulator of claim 1 , wherein in response to the sensed change in the current-level, the power amplification circuitry is to draw power from both the second input port and the first input port.

13. A voltage-regulation method involving a dual input low drop out voltage regulator providing a regulated voltage at an output port, wherein the voltage regulator comprises power amplification circuitry having a first input port coupled to a first power source and a first power stage coupled to the first input port, a second input port coupled to a second power source and a second power stage coupled to the second input port, wherein an output of the first power stage and an output of the second power stage are coupled to the output port, wherein the first power stage has at least a first intermediate power stage and a first power field-effect transistor (FET), and a second power stage has at least a second intermediate power stage and a second power FET, wherein at least the first power stage and the second power stage form FET circuitry, the method comprising:
operating the FET circuitry in a saturation mode while drawing power provided at the first input port from a first power source; and
sensing, via current-level switch circuitry coupled to the FET circuitry, a change in a current-level, wherein the sensed change in the current level is indicative of the first power FET being out of saturation or at a threshold of saturation used to maintain the FET circuitry in the saturation mode; and
in response to a sensed change in the current level, maintaining the saturation mode using the FET circuit by: switching from the first power stage coupled to the first input port to the second power stage coupled to the second input port, and further by; in response to the switch, the second power stage drawing power provided at the second port from the second power source and the source power FET transitioning to saturation, the FET circuitry maintaining the saturation mode.

14. The method of claim 13 , further including causing the power amplification circuitry to switch on-the-fly by switching from drawing power from the first input port to drawing power from the second input por

Assignees

• Nxp Bv

Inventors

• Sorace Christian Vincent
• Oddoart Ludovic
• Boitard Fabien

Classifications

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• G05F1/461

  using an operational amplifier as final control device · CPC title

• G05F1/565 Primary

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title

• G05F1/445

  being transistors in series with the load · CPC title