Apparatus and method for power management with a two-loop architecture

Patent metadata

Field	Value
Publication number	US-2016306374-A1
Application number	US-201514689600-A
Country	US
Kind code	A1
Filing date	Apr 17, 2015
Priority date	Apr 17, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.

First claim

We claim:

1 . An apparatus, comprising:
a power gate, coupled to a load, including a plurality of current sources; a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load; and a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current.

2 . The apparatus of claim 1 , wherein the plurality of current sources are coupled to a power source, and wherein the current control circuit includes a replica circuit to output an output voltage to the power gate to regulate the constant current based at least in part on a current limit of the one or more current sources.

3 . The apparatus of claim 1 , wherein the current control circuit comprises a replica circuit to output a bias voltage to the power gate and to regulate the bias voltage to a desired value of an output voltage of the power gate based at least in part on a voltage identity received by the current control loop.

4 . The apparatus of claim 3 , wherein the replica circuit comprises an amplifier to receive the voltage identity and a power supply, and to output the bias voltage.

5 . The apparatus of claim 4 , wherein the plurality of current sources comprise a plurality of transistors, wherein a first transistor of the plurality of transistors is to charge a gate of the first transistor to the bias voltage generated by the current control circuit.

6 . The apparatus of claim 4 , wherein the amplifier is a first amplifier, and wherein the replica circuit further comprises a second amplifier coupled to the first amplifier to receive the bias voltage and to buffer the bias voltage.

7 . The apparatus of claim 1 , wherein the voltage control circuit comprises an analog module to generate a digital code corresponding to an error signal based on a reference voltage received from a reference voltage source and a feedback voltage received from the power gate.

8 . The apparatus of claim 7 , wherein the voltage control circuit further comprises a digital controller, coupled to the analog module, to determine and select the one or more current sources based at least in part on the digital code corresponding to the error signal.

9 . The apparatus of claim 1 , wherein the voltage control circuit comprises a control loop with a gain that is independent of an output impedance of the power gate.

10 . The apparatus of claim 1 , wherein the current control circuit comprises a control loop with a gain that is independent of a number of the one or more current sources selected by the voltage control circuit.

11 . The apparatus of claim 1 , wherein the current control circuit comprises a control loop with a first speed, wherein the voltage control circuit includes a control loop with a second speed, wherein the second speed is faster than the first speed.

12 . The apparatus of claim 1 , wherein the current control circuit is to modulate a resistance of the power gate as a function of a dropout between a supply voltage and an output voltage of the power gate.

13 . A method, comprising:
determining, by a first control loop, a transistor in a power gate as an active current source to a load connected to the power gate; and regulating, by a second control loop, the transistor to output a constant current based at least in part on a current limit of the transistor.

14 . The method of claim 13 , further comprising:
modulating, by the second control loop, a bias voltage to a desired output voltage of the power gate based at least in part on a voltage identity received by the second control loop; and supplying, by the second control loop, the bias voltage to the transistor in the power gate.

15 . The method of claim 14 , wherein regulating further comprises charging a gate of the transistor to the bias voltage supplied by the second control loop.

16 . The method of claim 14 , wherein regulating further comprises discharging a gate to source capacitor and a gate to drain capacitor of the transistor based on the bias voltage.

17 . The method of claim 13 , further comprising:
comparing, by a first control loop, a reference voltage to a feedback voltage outputted from the power gate; and selecting, by a first control loop, one or more transistors of the power gate to be current sources to the load.

18 . The method of claim 13 , further comprising:
producing a gain of the first control loop independent of a number of the one or more transistors selected.

19 . The method of claim 13 , further comprising:
producing a gain of the first control loop independent of an output impedance of the power gate.

20 . The method of claim 13 , further comprising:
modulating, by a second control loop, a resistance of the power gate as a function of a dropout between a supply voltage and an output voltage of the power gate.

21 . A system on chip (SoC), comprising:
an integrated circuit (IC) die including a power island with a power gate coupled to a load, the power gate including a plurality of current sources; the IC die including a voltage control circuit, coupled to the power gate, to determine one or more current sources of the plurality of current sources to supply current to the load; and the IC die including a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current.

22 . The SoC of claim 21 , wherein the voltage control circuit includes a control loop with a gain that is independent of a number of the one or more current sources selected by the voltage control circuit.

23 . The SoC of claim 21 , wherein the current control circuit is to modulate a resistance of the power gate as a function of a dropout between a supply voltage and an output voltage of the power gate.

Assignees

• Intel Corp

Inventors

• Ghayal Rupak
• Patra Pradipta
• Muthukaruppan Ramnarayanan
• Chepuri Raghu Nandan

Classifications

• G05F3/02 Primary

  Regulating voltage or current · CPC title

• G05F1/59 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title