Dual mode voltage regulator with dynamic reconfiguration capability

Patent metadata

Field	Value
Publication number	US-9343963-B2
Application number	US-201113994810-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A dual mode voltage regulator according to one embodiment includes a passive regulator circuit; a switching regulator circuit; and a controller circuit configured to monitor operational parameters of the dual mode voltage regulator and selectively couple either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load. The selective coupling is based on the monitoring of parameters including current through the output load, voltage at the input voltage port and voltage at the output load as well as the availability of a system clock signal.

First claim

What is claimed is:

1. A dual mode voltage regulator, comprising:
an input voltage port;
an output voltage port;
a passive regulator circuit;
a switching regulator circuit; and
a controller circuit to monitor operational parameters of said dual mode voltage regulator and selectively couple one of said passive regulator circuit and said switching regulator circuit between said input voltage port and said output voltage port, said selective coupling based on said monitoring; and
wherein the controller circuit also to synchronize a first transition from the switching regulator circuit to the passive regulator circuit so that the first transition occurs at an end of a clock cycle of the switching regulator circuit, and to synchronize a second transition from the passive regulator circuit to the switching regulator circuit so that the second transition occurs at a start of the clock cycle of the switching regulator circuit.

2. The dual mode voltage regulator of claim 1 , wherein said switching regulator circuit comprises an upper power switch coupled between said input voltage port and said output voltage port; and a lower power switch coupled between said output voltage port and a ground; and wherein said passive regulator circuit is configured to control a pass gate, said pass gate employing said upper power switch of said switching regulator.

3. The dual mode voltage regulator of claim 2 , further comprising timing generation circuitry configured to provide a pulse width modulated (PWM) gating signal to said upper power switch and said lower power switch, and wherein the first and second transition of said selective coupling is synchronized with said PWM gating signal.

4. The dual mode voltage regulator of claim 1 , wherein said operational parameters include at least one of voltage at said input voltage port, voltage at said output voltage port, current through a load coupled to said output voltage port and presence of a system clock signal.

5. The dual mode voltage regulator of claim 1 , wherein said controller circuit is further configured to couple said switching regulator circuit between said input voltage port and said output voltage port in response to determining that a current through said load exceeds a first pre-determined threshold.

6. The dual mode voltage regulator of claim 1 , wherein said controller circuit is further configured to couple said passive regulator circuit between said input voltage port and said output voltage port in response to detecting the absence of a system clock signal.

7. The dual mode voltage regulator of claim 1 , wherein said controller circuit is further configured to couple said switching regulator circuit between said input voltage port and said output voltage port in response to determining that a ratio of a voltage at said input voltage port to a voltage at said output voltage port exceeds a second pre-determined threshold.

8. The dual mode voltage regulator of claim 1 , wherein said switching regulator circuit is configured as a buck voltage regulator and said passive regulator circuit is configured as a low drop-out (LDO) voltage regulator.

9. A method for providing dual mode voltage regulation, said method comprising:
monitoring operational parameters of a passive voltage regulator and a switching voltage regulator;
selectively coupling one of said passive voltage regulator and said switching voltage regulator between an input voltage port and an output voltage port, said selective coupling based on said monitoring;
synchronizing a first transition from the switching regulator circuit to the passive regulator circuit so that the first transition occurs at an end of a clock cycle of the switching regulator circuit, and
synchronizing a second transition from the passive regulator circuit to the switching regulator circuit so that the second transition occurs at a start of the clock cycle of the switching regulator circuit.

10. The method of claim 9 , wherein said operational parameters include at least one of voltage at said input voltage port, voltage at said output voltage port, current through a load coupled to said output voltage port and presence of a system clock signal.

11. The method of claim 9 , further comprising providing a switch that is operable as a power switch associated with said switching voltage regulator and as a pass gate associated with said passive voltage regulator.

12. The method of claim 11 , further comprising generating a PWM gating signal to control said switch and the first and second transitioning of said selective coupling is in synchronization with said PWM gating signal.

13. The method of claim 9 , further comprising coupling said switching voltage regulator between said input voltage port and said output voltage port in response to determining that a current through a load coupled to said output voltage port exceeds a first pre-determined threshold.

14. The method of claim 9 , further comprising coupling said passive voltage regulator between said input voltage port and said output voltage port in response to detecting the absence of a system clock signal.

15. The method of claim 9 , further comprising coupling said switching voltage regulator between said input voltage port and said output voltage port in response to determining that a ratio of a voltage at said input voltage port to a voltage at said output voltage port exceeds a second pre-determined threshold.

16. A computer-readable storage device having instructions stored thereon which when executed by a processor result in the following operations for providing dual mode voltage regulation, said operations comprising:
monitor operational parameters of a passive voltage regulator and a switching voltage regulator;
selectively coupling one of said passive voltage regulator and said switching voltage regulator between an input voltage port and an output voltage port, said selective coupling based on said monitoring;
synchronize a first transition from the switching regulator circuit to the passive regulator circuit so that the first transition occurs at an end of a clock cycle of the switching regulator circuit, and
synchronize a second transition from the passive regulator circuit to the switching regulator circuit so that the second transition occurs at a start of the clock cycle of the switching regulator circuit.

17. The computer-readable storage device of claim 16 , wherein said operational parameters include at least one of voltage at said input voltage port, voltage at said output voltage port, current through a load coupled to said output voltage port and presence of a system clock signal.

18. The computer-readable storage device of claim 16 , wherein said operations further comprise generating a PWM gating signal to control said switching voltage regulator and transitioning said selective coupling in synchronization with said PWM gating signal.

19. The computer-readable storage device of claim 16 , wherein said operations further comprise coupling said switching voltage regulator between said input voltage port and said output voltage port in response to determining that a current through a load coupled to said output voltage port exceeds a first pre-determined threshold.

20. The computer-readable storage device of claim 16 , wherein said operations further comprise coupling said passive voltage regulator between said input voltage port and said output voltage port in response to detecting the absence of a system clock signal.

21. The computer-readable

Assignees

• Cowley Nicholas P
• Talbot Andrew D
• Ali Isaac
• Pinson Keith
• Perry Colin L
• Aitken Matthew T
• Kan Chi Man
• Mudd Mark S
• Spinks Stephen J
• Martin Alan J
• Barber William L
• Intel Corp

Inventors

• Cowley Nicholas P
• Talbot Andrew D
• Ali Isaac
• Pinson Keith
• Perry Colin L
• Aitken Matthew T
• Kan Chi Man
• Mudd Mark S
• Spinks Stephen J
• Martin Alan J
• Barber William L

Classifications

• G05F1/46 Primary

  wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) · CPC title

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M2001/0045

  Electricity · mapped topic

• H02M1/0045

  Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode · CPC title