Aperture structure on semiconductor component backside to alleviate delamination in stacked packaging

Patent metadata

Field	Value
Publication number	US-11289395-B2
Application number	US-202016821860-A
Country	US
Kind code	B2
Filing date	Mar 17, 2020
Priority date	Apr 18, 2019
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A process includes forming one or more apertures on a component backside, creating a vacuum in a mold chase, and engaging the component backside with a mold compound in the mold chase. The one or more apertures form an aperture structure. The aperture structure may include multiple apertures parallel or orthogonal to each other. The apertures have an aperture width, aperture depth, and aperture pitch. These characteristics may be altered to minimize the likelihood of trapped air remaining after creating the vacuum in the mold chase.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first semiconductor component having a backside portion positioned on a second semiconductor component; and
wherein the backside portion of the first semiconductor component includes one or more apertures to allow air to flow between the first semiconductor component and the second semiconductor component, wherein each aperture has an aperture width of between about 10 μm to about 20 μm, and wherein parallel apertures have an aperture pitch of between about 100 μm to about 1 mm.

2. The semiconductor package of claim 1 , wherein the one or more apertures comprises a first set of multiple parallel apertures.

3. The semiconductor package of claim 2 , wherein the first set of multiple parallel apertures have an aperture pitch, the aperture pitch being lesser toward a center of the backside portion.

4. The semiconductor package of claim 2 , wherein the one or more apertures further comprises a second set of multiple parallel apertures orthogonal to the first set of multiple parallel apertures forming a matrix of apertures.

5. The semiconductor package of claim 1 , wherein the backside portion comprises a component length longer than a component width, the one or more apertures comprising a first aperture bisecting the backside portion and extending from edge to edge across the component length.

6. A semiconductor package, comprising:
a first semiconductor component having a backside portion positioned on a second semiconductor component;
wherein the backside portion of the first semiconductor component includes one or more apertures to allow air to flow between the first semiconductor component and the second semiconductor component;
wherein the backside portion comprises a component length longer than a component width, the one or more apertures comprising a first aperture bisecting the backside portion and extending from edge to edge across the component length; and
wherein the one or more apertures further comprises a second aperture bisecting the backside portion and extending from edge to edge of the component width.

7. The semiconductor package of claim 6 , wherein the first aperture and the second aperture are orthogonal apertures.

8. The semiconductor package of claim 6 , wherein the first aperture and the second aperture are not orthogonal.

Assignees

• Western Digital Tech Inc

Inventors

• Yan Junrong
• Chin Chee Keong
• Lu Xin

Classifications

• H10P72/04

  Apparatus for manufacture or treatment · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title