Integrated circuit(s) with anti-glitch canary circuit(s)

Patent metadata

Field	Value
Publication number	US-11288405-B2
Application number	US-201817058152-A
Country	US
Kind code	B2
Filing date	Oct 25, 2018
Priority date	Oct 25, 2018
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

An IC comprising functional circuit to perform primary functions of the IC is provided. The functional circuit is to enable electrical signals to propagate through it within a timing constraint of the functional circuit. The IC comprises at least one canary circuit used for detecting glitch attacks on the circuit. Electrical signals are to propagate through the canary circuit(s) within a defined timing constraint of the canary circuit(s). The canary circuit is to provide a signal path designed such that in the event of a timing constraint of the functional circuit(s) is violated due to a glitch attack, also the timing constraint of the canary circuit(s) is violated.

First claim

The invention claimed is:

1. An integrated circuit comprising:
a functional circuit to perform primary functions of the integrated circuit, wherein electrical signals propagate through the functional circuit with a first propagation delay that is within a timing constraint of the integrated circuit based on a clock signal of the integrated circuit;
a strict canary circuit through which electrical signals propagate with a second propagation delay approximating the timing constraint of the integrated circuit, where the strict canary circuit detects glitches in the clock that violate the timing constraint;
a relaxed canary circuit through which electrical signals propagate with a third propagation delay between the first propagation delay and the second propagation delay, where the relaxed canary circuit detects glitches in the clock signal approximating the first propagation delay of the functional circuit; and
monitoring logic to:
identify a first glitch in the clock signal as unlikely to have compromised the functional circuit based on the glitch being detected by the strict canary circuit and undetected by the relaxed canary circuit, and
identify a second glitch in the clock signal as likely to have compromised the functional circuit based on the glitch being detected by the strict canary circuit and the relaxed canary circuit.

2. The integrated circuit of claim 1 , wherein the monitoring logic is to send an intrusion-detection signal in response to identification of the second glitch to initiate a counteraction against a glitch attack.

3. The integrated circuit of claim 1 , wherein a plurality of canary circuits are distributed over the integrated circuit.

4. The integrated circuit of claim 1 , wherein each of the strict canary circuit and the relaxed canary circuit is implemented in a block of the integrated circuit which is separate from the functional circuit.

5. The integrated circuit of claim 1 , wherein each of the strict canary circuit and the relaxed canary circuit comprises standard logic gates and is to perform calculation operations,
wherein a violation of the timing constraint is deemed to have occurred in response to a result of the calculation operations not matching an expected result of the calculation operations.

6. The integrated circuit of claim 1 , wherein each of the strict canary circuit and the relaxed canary circuit comprises standard logic gates, including a succession of inverters, to perform calculation operations, wherein a violation of a timing constraint is deemed to have occurred in response to a result of the calculation operations not matching an expected result of the calculation operations.

7. The integrated circuit of claim 1 , wherein the glitches in the clock signal are caused by a voltage glitch.

8. The integrated circuit of claim 1 , wherein the integrated circuit comprises a storage medium on which a firmware-signature is stored and wherein each of the strict canary circuit and the relaxed canary circuit is placed adjacent to circuits for accessing said storage medium on which the firmware signature is stored.

9. The integrated circuit of claim 1 , wherein the integrated circuit comprises a cryptographic engine and wherein each of the strict canary circuit and the relaxed canary circuit is placed in the integrated circuit adjacent to at least one of the input and the output of said cryptographic engine.

10. A method of handling a glitch attack on an integrated circuit, the method comprising:
performing primary functions of the integrated circuit by a functional circuit, wherein the functional circuit enables electric signals to propagate through the functional circuit with a first propagation delay that is within a timing constraint of the integrated circuit; and
detecting a glitch attack based on identification of a glitch in a clock signal identified by both a strict canary circuit and a relaxed canary circuit,
wherein the strict canary circuit propagates electrical signals with a second propagation delay approximating the timing constraint of the integrated circuit, and
wherein the relaxed canary circuit propagates electrical signals with a third propagation delay between the first propagation delay and the second propagation delay.

11. The method of claim 10 , further comprising:
sending an intrusion-detection signal to initiate a counteraction in response to the glitch attack.

12. The method of claim 10 , wherein each of the strict canary circuit and the relaxed canary circuit comprises standard logic gates, including a succession of inverters, to perform calculation operations.

13. The method of claim 10 , wherein detecting the glitch attack comprises detecting a voltage glitch attack.

14. The method of claim 10 , wherein the integrated circuit comprises a storage medium on which a firmware-signature is stored and wherein each of the strict canary circuit and the relaxed canary circuit is placed adjacent to circuits for accessing said storage medium on which the firmware signature is stored.

15. The method of claim 10 , wherein the integrated circuit comprises a cryptographic engine and wherein each of the strict canary circuit and the relaxed canary circuit is placed in the integrated circuit adjacent to at least one of the input and the output of said cryptographic engine.

Assignees

• Hewlett Packard Development Co

Inventors

• Belgarric Pierre
• Plaquin David
• Cohen Eugene
• Gunning Chris R

Classifications

• G06F21/60

  Protecting data · CPC title

• G06K19/073

  Special arrangements for circuits, e.g. for protecting identification code in memory (protection against unauthorised use of computer memory G06F12/14) · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F21/75 Primary

  by inhibiting the analysis of circuitry or operation · CPC title

• G06F21/76 Primary

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title