Circuitry and method for timing speculation via toggling functional critical paths

Patent metadata

Field	Value
Publication number	US-9564883-B1
Application number	US-201514791443-A
Country	US
Kind code	B1
Filing date	Jul 4, 2015
Priority date	Apr 13, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Toggling functional critical path timing sensors measure delays in toggling functional critical paths that are replicas of actual critical paths or representations of worst-case delay paths. A Toggle flip-flop or Linear-Feedback-Shift Register (LFSR) drives high-transition-density test patterns to the toggling functional critical paths. When a toggling functional critical path's delay fails to meet set-up timing requirement to a next register, the toggling functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. A margin delay buffer adds a delay to the toggling functional critical path before being clocked into an early capture flip-flop. A reference register receives the test pattern without the delay of the toggling functional critical path, and an exclusive-OR (XOR) gate compares outputs of reference and early capture flip-flops to generate timing failure signals to the controller.

First claim

We claim:

1. A timing-failure-predicting integrated circuit comprising:
a toggling pattern generator that generates a toggle pattern having a high density of transitions;
a plurality of toggling functional critical paths that receives the toggle pattern generated by the toggling pattern generator;
a plurality of toggling functional critical path timing sensors, each receiving an output of a toggling functional critical path in the plurality of toggling functional critical paths;
a plurality of fail signals generated by the plurality of toggling functional critical path timing sensors, wherein a fail signal is generated when a delay through a toggling functional critical path exceeds a timing requirement; and
a VDD adjustment controller that receives the fail signals generated by the plurality of toggling functional critical path timing sensors, the VDD adjustment controller causing a power-supply voltage to the plurality of toggling functional critical paths and to the plurality of toggling functional critical path timing sensors to be increased when the fail signal is received, the VDD adjustment controller causing the power-supply voltage to be reduced when no fail signal is received for a period of time,
wherein the power-supply voltage is adjusted to compensate for timing failures detected through the toggling functional critical paths.

2. The timing-failure-predicting integrated circuit of claim 1 wherein the timing requirement is a set-up time to a clocked register plus a margin delay of a margin delay buffer;
wherein the fail signals are generated when delays through the toggling functional critical path plus the margin delay fails to meet the set-up time to the clocked register.

3. The timing-failure-predicting integrated circuit of claim 2 wherein the toggling functional critical path timing sensor comprises:
a first register that receives an output of a toggling functional critical path;
a compare gate that compares an output of the first register to the output of the toggling functional critical path to generate the fail signal when the output of the first register does not match the output of the toggling functional critical path;
a second register that receives the output of the compare gate to generate the fail signal, the second register being clocked by a delayed clock.

4. The timing-failure-predicting integrated circuit of claim 2 wherein the toggling functional critical path timing sensor comprises:
a margin delay buffer that receives an output of a toggling functional critical path;
a first register that receives an output of the margin delay buffer;
a second register that receives an input of the toggling functional critical path; and
a compare gate that compares an output of the first register to an output of the second register to generate the fail signal when the output of the first register does not match the output of the second register.

5. The timing-failure-predicting integrated circuit of claim 4 wherein a margin delay through the margin delay buffer is variable.

6. The timing-failure-predicting integrated circuit of claim 4 wherein the toggling pattern generator is a toggle flip-flop that generates a transition on an output for each clock period.

7. The timing-failure-predicting integrated circuit of claim 4 wherein the toggling pattern generator is a Linear-Feedback-Shift Register (LFSR).

8. The timing-failure-predicting integrated circuit of claim 7 wherein a multi-path toggling functional critical path in the plurality of toggling functional critical paths comprises a plurality of converging paths that converge and are combined before being applied to one of the plurality of toggling functional critical path timing sensors;
wherein the LFSR generates a plurality of outputs that are applied to the plurality of converging paths.

9. The timing-failure-predicting integrated circuit of claim 4 wherein the toggling functional critical paths comprise copies of functional critical paths that carry user data or control information during a normal operating mode of the timing-failure-predicting integrated circuit.

10. The timing-failure-predicting integrated circuit of claim 3 wherein the toggling functional critical paths comprise representational critical paths having a string of gates with a number of gates exceeding a maximum number of gates in any functional critical path in the timing-failure-predicting integrated circuit, or a gate with a fan-out exceeding a maximum fan-out of any functional critical path in the timing-failure-predicting integrated circuit.

11. The timing-failure-predicting integrated circuit of claim 10 wherein the toggling functional critical paths comprise representational critical paths that comprise:
a string of gates;
a gate with a high fan-out;
a larger buffer with a high capacitive load; and
a mux that receives outputs from the string of gates, from the gate with the high fan-out, and from the larger buffer, the mux selecting an output for testing by the toggling functional critical path timing sensor.

12. The timing-failure-predicting integrated circuit of claim 4 further comprising:
a plurality of registers for storing internal signals in response to a clock;
combinatorial logic between inputs and outputs of the plurality of registers; and
a plurality of functional critical paths being among a top 10% of paths in the combinatorial logic sorted by delay;
wherein the plurality of toggling functional critical paths are replicas of paths in the plurality of functional critical paths that are among the top 10% of paths in the combinatorial logic sorted by delay.

13. A process-compensating timing adjustor comprising:
a toggling pattern generator that generate patterns that accelerate testing;
a plurality of toggling functional critical paths that receive the patterns generated by the toggling pattern generator;
a plurality of toggling functional critical path timing sensors, each toggling functional critical path timing sensor receiving a delayed output from one of the plurality of toggling functional critical paths that is delayed by a variable delay buffer, each toggling functional critical path timing sensor activating a timing failure signal when the delayed output does not meet a set-up time to a clocked register;
a power-voltage controller that receives the timing failure signals from the plurality of toggling functional critical path timing sensors, the power-voltage controller increasing a power-supply voltage when a timing failure signal is received, the power-voltage controller decreasing the power-supply voltage when the timing failure signal is not received over a period of time,
whereby the power-supply voltage is adjusted in response to timing failures.

14. The process-compensating timing adjustor of claim 13 wherein the toggling pattern generator is a toggle flip-flop.

15. The process-compensating timing adjustor of claim 13 wherein the toggling pattern generator is a Linear-Feedback-Shift Register (LFSR).

16. The process-compensating timing adjustor of claim 13 wherein the toggling functional critical paths comprise copies of functional critical paths that carry user data or control information during a normal operating mode of the process-compensating timing adjustor.

17. The process-compensating timing adjustor of claim 13 wherein the toggling functional critical paths comprise representational critical paths having a string of gates with a number of gates exceeding a maximum number of gates in any functional critical path in an integrated circuit, or a gate wi

Assignees

• Abreezio LLC
• Qualcomm Inc

Inventors

• Quinton Bradley
• McClements Trent
• Hughes Andrew
• Taneja Sanjiv

Classifications

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• H03K5/13 Primary

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H03K2005/00019

  Variable delay · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• H03K3/0375

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title