Method for characterizing the operation of a digital electronic circuit and digital electronic circuit

Patent metadata

Field	Value
Publication number	US-9823301-B2
Application number	US-201515117017-A
Country	US
Kind code	B2
Filing date	Feb 9, 2015
Priority date	Feb 7, 2014
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A method is presented for characterizing a digital circuit for determining an optimum operating point of the digital circuit. The digital circuit includes sequential elements; conducting data paths; a clock tree; a time fault sensor receiving as input a data signal and configured to detect during a detection window a transition of the data signal; and a system for setting first and second operating parameters of the circuit. The method includes a) activating a conducting data path leading to the sequential element coupled to the sensor; b) determining, for a given value of the first parameter, a first value of the second parameter from which the sensor detects a transition of the data signal during the detection window, the values of the first and second parameters defining an operating point of the circuit; and c) correcting the operating point.

First claim

The invention claimed is:

1. A method for calibrating a digital circuit comprising:
a plurality of sequential elements;
data conducting paths between the sequential elements;
a clock tree delivering a clock signal for clocking the sequential elements; and
a time fault sensor of preventive type coupled to one of the sequential elements, receiving as input a data signal arriving at the sequential element and configured to detect during a detection window a transition of the data signal;
means for setting at least one first and one second operating parameter of the digital circuit;
the calibration method comprising:
a) activating a data conducting path up to the sequential element coupled to the sensor;
b) determining, for a given value of the first parameter, a first value of the second parameter from which the sensor detects a transition of the data signal during the detection window, said values of the first and second parameters defining a detection operating point of the digital circuit;
c) determining, for said value of the first parameter, a second value of the second parameter above which the digital circuit is in malfunction;
d) calculating, for the detection operating point, a correction margin equal to the difference between the first and second values of the second parameter.

2. The method according to claim 1 , wherein steps a) to d) are carried out for a plurality of control circuits having a structure identical to the digital circuit, for a same given value of the first parameter, so as to obtain several correction margins relative to the sensor, and further comprising a step of determining an optimum correction margin associated with the value of the first parameter of the detection operating points from correction margins relative to the sensor.

3. The method according to claim 2 , wherein the optimum correction margin is an arithmetic mean of the correction margins relative to the sensor.

4. The method according to claim 2 , wherein the optimum correction margin is the lowest of the correction margins relative to the sensor.

5. The method according to claim 1 , wherein one of the first and second parameters is chosen from among a frequency and a period of the clock signal and wherein the other of the first and second parameters is chosen from among a supply voltage and a bias voltage of the digital circuit.

6. The method according to claim 5 , wherein the second parameter is the frequency of the clock signal and each correction margin is a frequency margin.

7. The method according to claim 5 , wherein the second parameter is the period of the clock signal and each correction margin is a time margin.

8. The method according to claim 5 , wherein the second parameter is chosen from among the supply voltage and the bias voltage of the digital circuit and each correction margin is a voltage margin.

9. The method according to claim 1 , wherein the second value of the second parameter is obtained by activating a critical data conducting path and by modifying progressively the second parameter up to causing a time violation of the data signal received by the sequential element arranged on the critical path, with respect to an active edge of the clock signal.

10. The method according to claim 1 , wherein steps a) to d) are carried out for several values of the first parameter.

11. The method according to claim 1 , wherein the detection window is located before an active edge of the clock signal.

12. The method according to claim 1 , wherein the detection window is between 10% and 50% of a period of the clock signal.

13. A method for characterizing an integrated circuit consisting in determining at a given instant of the life of the circuit an optimum operating point of the digital circuit comprising:
a plurality of sequential elements;
data conducting paths between the sequential elements;
a clock tree delivering a clock signal for clocking the sequential elements; and
a time fault sensor of preventive type coupled to one of the sequential elements, receiving as input a data signal arriving at the sequential element and configured to detect, during a detection window, a transition of the data signal,
means for setting at least one first and one second operating parameter of the digital circuit,
the characterization method comprising:
e) activating a data conducting path up to the sequential element coupled to the sensor,
f) determining, for a given value of the first parameter, a first value of the second parameter from which the sensor detects a transition of the data signal during the detection window, said values of the first and second parameters defining a detection operating point of the digital circuit,
g) determining an optimum operating point associated with the detection operating point, by adding to the first value of the second parameter, a predetermined correction margin in relation with a limit value of the second parameter which would lead to a malfunction of the digital circuit, for the given value of the first parameter, said correction margin being associated with the given value of the first parameter of the detection operating point.

14. The method according to claim 13 , in which, when the circuit comprises a plurality of time fault sensors of preventive type each coupled to one of the sequential elements, steps e) to g) are carried out for each sensor, so as to obtain a plurality of corrected operating points having the same value of the first parameter, the method further comprising a step of determining, from the plurality of corrected operating points, a single optimum operating point associated with the considered value of the first parameter.

15. The method according to claim 14 , wherein the single optimum operating point is defined by said value of the first parameter and an arithmetic mean of said values of the second parameter of the plurality of corrected operating points.

16. The method according to claim 14 , wherein the second parameter is a frequency of the clock signal and the single optimum operating point is defined by said value of the first parameter and the lowest of said values of the second parameter of the plurality of corrected operating points.

17. The method according to claim 14 , wherein the second parameter is the supply voltage (V) of the digital circuit and the single optimum operating point is defined by said value of the first parameter and the highest of said values of the second parameter of the plurality of corrected operating points.

18. The method according to claim 13 , wherein the predetermined correction margin is memorised in a memory of the circuit or is calculated from a functional relation memorised in the circuit; the memorised values or the functional relation being obtained by the implementation of a calibration method.

19. The method according to claim 13 , wherein steps e) to g) are carried out for several values of the first parameter.

20. A digital electronic circuit comprising:
a plurality of sequential elements;
data conducting paths between the sequential elements, at least one of the data conducting paths being critical in terms of data propagation delay,
a clock tree delivering a clock signal for clocking the sequential elements; and
a time fault sensor of preventive type coupled to one of the sequential elements, receiving as input a data signal arriving at the sequential element and configured to detect, during a detection window, a transition of the data signal,
means for setting at least one first and one sec

Assignees

• Commissariat Energie Atomique
• Commissariat L Energie Atomique Et Aux Energies Alternatives

Inventors

• Miro Panades Ivan

Classifications

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/3016 Primary

  Delay or race condition test, e.g. race hazard test · CPC title

• H03K2005/00013

  Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse · CPC title

• H03K5/13

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title