Scan flip-flop and scan test circuit including the same

Patent metadata

Field	Value
Publication number	US-11287474-B2
Application number	US-201916552109-A
Country	US
Kind code	B2
Filing date	Aug 27, 2019
Priority date	Oct 2, 2014
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

First claim

What is claimed is:

1. A scan flip-flop comprising:
an input unit; and
a flip-flop comprising a master latch and a slave latch, the flip-flop connected to the input unit,
wherein the flip-flop is implemented to include a plurality of cross coupled structures, and
wherein at least one of the plurality of cross coupled structures is implemented in an area corresponding to a 2 CPP (contact poly pitch).

2. The scan flip-flop of claim 1 , wherein the at least one of the plurality of cross coupled structures comprises:
a plurality of first active fins which extend along a first direction and are disposed in parallel in a second direction substantially vertical to the first direction;
a plurality of second active fins which extend along the first direction and are disposed in parallel in the second direction;
first and second conductive lines extending in parallel across the plurality of first active fins;
third and fourth conductive lines extending in parallel across the plurality of second active fins;
a cutout region disposed between the first conductive line and the third conductive line, and between the second conductive line and the fourth conductive line; and
a diagonal contact which traverses the cutout region and connects the second conductive line and third conductive line,
wherein the first conductive line is aligned with the third conductive line, and
the second conductive line is aligned with the fourth conductive line.

3. The scan flip-flop of claim 2 , wherein the at least one of the plurality of cross coupled structures further comprises at least one dummy fin which extends along the first direction and is disposed between the plurality of first active fins and the plurality of second active fins.

4. The scan flip-flop of claim 1 , wherein the master latch includes a first tri-state inverter and a second tri-state inverter which share a first output node and face each other.

5. The scan flip-flop of claim 4 , wherein the first tri-state inverter comprises a first pull-up unit, a first pull-down unit, a first PMOS transistor connected between the first pull-up unit and the first output node, and a first NMOS transistor connected between the first output node and the first pull-down unit, and
the second tri-state inverter comprises a second pull-up unit, a second pull-down unit, a second PMOS transistor connected between the second pull-up unit and the first output node, and a second NMOS transistor connected between the first output node and the second pull-down unit.

6. The scan flip-flop of claim 5 , wherein a gate of the first PMOS transistor is electrically connected to a gate of the second NMOS transistor, a gate of the first NMOS transistor is electrically connected to a gate of the second PMOS transistor, and the first and second PMOS transistors and the first and second NMOS transistors constitute a first cross coupled unit.

7. A scan flip-flop comprising:
an input unit; and
a flip-flop comprising a master latch and a slave latch, the flip-flop connected to the input unit,
wherein the flip-flop is implemented to include a plurality of cross coupled structures, and
wherein at least one of the plurality of cross coupled structures is implemented in an area corresponding to a 3 CPP (contact poly pitch).

8. A scan flip-flop comprising:
an input unit; and
a flip-flop comprising a master latch and a slave latch, the flip-flop connected to the input unit,
wherein the flip-flop is implemented to include a plurality of cross coupled structures, and
wherein the input unit comprises a multiplexer implemented to include a cross coupled structure.

9. A flip-flop comprising:
a plurality of first active fins which extend along a first direction and are disposed in parallel in a second direction substantially vertical to the first direction;
a plurality of second active fins which extend along the first direction and are disposed in parallel in the second direction;
a first conductive line and a second conductive line that extend in parallel across the plurality of first active fins;
a third conductive line and a fourth conductive line that extend in parallel across the plurality of second active fins;
a cutout region disposed between the first conductive line and the third conductive line, and between the second conductive line and the fourth conductive line; and
a diagonal contact which traverses the cutout region and connects the second conductive line and third conductive line,
wherein the first conductive line is aligned with the third conductive line, and
the second conductive line is aligned with the fourth conductive line.

10. The flip-flop of claim 9 , further comprising:
at least one dummy fin which extends along the first direction and is disposed between the plurality of first active fins and the plurality of second active fins.

11. The flip-flop of claim 9 , further comprising:
a first contact disposed between the first conductive line and the second conductive line;
a first via on the first contact;
a second contact disposed between the third conductive line and the fourth conductive line; and
a second via on the second contact.

12. The flip-flop of claim 9 , further comprising:
a first gate contact on the first conductive line;
a second gate contact on the second conductive line;
a third gate contact on the third conductive line; and
a fourth gate contact on the fourth conductive line,
wherein the first and second gate contacts are disposed to be spaced apart from a lower boundary line of the flip-flop by a first distance, and
the third and fourth gate contacts are disposed to be spaced apart from the lower boundary line of the flip-flop by a second distance.

13. The flip-flop of claim 12 , wherein a height from a substrate to an upper surface of the diagonal contact is substantially the same as a height from the substrate to an upper surface of the first gate contact or a height from the substrate to an upper surface of the fourth gate contact.

14. The flip-flop of claim 9 , further comprising:
a power line that extends along the first direction and is disposed adjacent to the plurality of first active fins in the second direction; and
a ground line that extends along the first direction and is disposed adjacent to the plurality of second active fins in the second direction.

15. The flip-flop of claim 9 , wherein the plurality of first active fins, the plurality of second active fins, the first to fourth conductive lines, the cutout region, and the diagonal contact correspond to a cross coupled structure.

16. A semiconductor device including a cross coupled structure, the cross coupled structure comprising:
a plurality of first active fins which extend along a first direction and are disposed in parallel in a second direction substantially vertical to the first direction;
a plurality of second active fins which extend along the first direction and are disposed in parallel in the second direction;
a first conductive line and a second conductive line that extend in parallel across the plurality of first active fins; and
a third conductive line and a fourth conductive line that extend in parallel across the plurality of second active fins,
wherein the cross coupled structure is implemented in an area corresponding to a 2 CPP (contact poly pitch).

17. The semiconductor device of claim 16 , further comprising:
at least one dummy fin which extends along the first direction and is disposed between the plurality of first active fins and the plurality of second active fins.

18

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ha-Young
• Cho Sung-We
• Lee Dal-Hee
• Lee Jae-Ha

Classifications

• H03K3/35625

  using complementary field-effect transistors · CPC title

• G01R31/318541 Primary

  Scan latches or cell details · CPC title