Scan flip-flop and scan test circuit including the same

Patent metadata

Field	Value
Publication number	US-9753086-B2
Application number	US-201514873634-A
Country	US
Kind code	B2
Filing date	Oct 2, 2015
Priority date	Oct 2, 2014
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop os configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

First claim

What is claimed is:

1. A scan flip-flop comprising:
an input unit configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode; and
a flip-flop configured to latch the internal signal according to a clock signal, the flip-flop including a cross coupled structure that includes first and second tri-state inverters which share a first output node, the first tri-state inverter receiving a first input signal and first and second control signals, and the second tri-state inverter receiving a second input signal and the first and second control signals,
wherein the cross couple structure includes first and second active regions and a dummy region interposed between the first and second active regions in a layout view of the cross coupled structure, and first and second conductive lines extending in parallel across the first and second active regions and the dummy region,
wherein the cross coupled structure further includes a cutout region in the dummy region for separating the first conductive line into a first portion and a second portion, and for separating the second conductive line into a third portion and a fourth portion, and
wherein the cross couple structure further includes a diagonal contact which traverses the cutout region and connects the first portion of the first conductive line and the fourth portion of the second conductive line, and a via for applying one of the first and second control signals to the diagonal contact.

2. The scan flip-flop of claim 1 , wherein the flip-flop comprises:
a master latch including the first and second tri-state inverters; and
a slave latch connected to the master latch.

3. The scan flip-flop of claim 2 , wherein
the first tri-state inverter comprises a first pull-up unit, a first pull-down unit, a first PMOS transistor connected between the first pull-up unit and the first output node, and a first NMOS transistor connected between the first output node and the first pull-down unit, and
the second tri-state inverter comprises a second pull-up unit, a second pull-down unit, a second PMOS transistor connected between the second pull-up unit and the first output node, and a second NMOS transistor connected between the first output node and the second pull-down unit.

4. The scan flip-flop of claim 3 , wherein a gate of the first PMOS transistor is electrically connected to a gate of the second NMOS transistor, a gate of the first NMOS transistor is electrically connected to a gate of the second PMOS transistor, and the first and second PMOS transistors and the first and second NMOS transistors constitute a first cross coupled unit.

5. The scan flip-flop of claim 3 , wherein
an inversion clock signal generated by inverting the clock signal is applied to the gate of the first NMOS transistor and the gate of the second PMOS transistor, and
a buffered clock signal generated by inverting the inversion clock signal is applied to the gate of the first PMOS transistor and the gate of the second NMOS transistor.

6. The scan flip-flop of claim 2 , wherein the input unit comprises a multiplexer configured to include third and fourth tri-state inverters that share a second output node and face each other.

7. The scan flip-flop of claim 6 , wherein
the third tri-state inverter comprises a third pull-up unit and a third pull-down unit which are controlled according to the data input signal, a third PMOS transistor connected between the third pull-up unit and the second output node, and a third NMOS transistor connected between the second output node and the third pull-down unit, and
the fourth tri-state inverter comprises a fourth pull-up unit and a fourth pull-down unit which are controlled according to the scan input signal, a fourth PMOS transistor connected between the fourth pull-up unit and the second output node, and a fourth NMOS transistor connected between the second output node and the fourth pull-down unit.

8. The scan flip-flop of claim 7 , wherein a gate of the third PMOS transistor is electrically connected to a gate of the fourth NMOS transistor, a gate of the fourth NMOS transistor is electrically connected to a gate of the third PMOS transistor, and the third and fourth PMOS transistors and the third and fourth NMOS transistors constitute a second cross coupled unit.

9. The scan flip-flop of claim 7 , wherein the first and fourth tri-state inverters share a power terminal and a ground terminal.

10. The scan flip-flop of claim 2 , wherein the slave latch comprises:
a transmission gate configured to transfer an output signal of the master latch; and
a fifth tri-state inverter configured to share a third output node with the transmission gate.

11. The scan flip-flop of claim 10 , wherein
the fifth tri-state inverter comprises a fifth pull-up unit, a fifth pull-down unit, a fifth PMOS transistor connected between the fifth pull-up unit and the third output node, and a fifth NMOS transistor connected between the third output node and the fifth pull-down unit,
the transmission gate comprises a sixth PMOS transistor, including a gate electrically connected to a gate of the fifth NMOS transistor, and a sixth NMOS transistor including a gate electrically connected to a gate of the fifth PMOS transistor, and
the fifth and sixth PMOS transistors and the fifth and sixth NMOS transistors constitute a third cross coupled unit.

12. A scan flip-flop comprising:
an input unit configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode; and
a flip-flop configured to latch the internal signal according to a clock signal, the flip-flop including a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other,
wherein the flip-flop comprises a master latch including the first and second tri-state inverters, and a slave latch connected to the master latch, and
wherein the master latch further comprises a reset switch connected between the first output node and a ground terminal, the reset switch being controlled according to a reset control signal.

13. The scan flip-flop of claim 12 , wherein the master latch further comprises a set switch connected between a power terminal and the first output node, the set switch being controlled according to a set control signal.

14. The scan flip-flop of claim 2 , wherein the master latch further comprises:
a set switch connected between a power terminal and the first output node, the set switch being controlled according to a set control signal; and
a reset switch connected between the first output node and a ground terminal, the reset switch being controlled according to a reset control signal.

15. A scan test circuit comprising:
a sequential circuit unit configured to include first and second scan flip-flops, at least one of the first and second scan flip-flops including a flip-flop that includes a cross coupled structure including first and second tri-state inverters which share a first output node; and
a combinational circuit unit configured to include first and second combinational logic circuits, the first combinational logic circuit supplying a first data input signal, generated by performing a logic operation on pieces of data, to the first scan flip-flop, and the second combinational logic circuit supplying a second data input signal, generated by performing a logic operation on an output signal of the first scan flip-flop, to the second

Assignees

• Kim Ha-Young
• Cho Sung-Wee
• Lee Dal-Hee
• Lee Jae-Ha
• Samsung Electronics Co Ltd

Inventors

• Kim Ha-Young
• Cho Sung-Wee
• Lee Dal-Hee
• Lee Jae-Ha

Classifications

• G01R31/318541 Primary

  Scan latches or cell details · CPC title

• H03K3/35625

  using complementary field-effect transistors · CPC title