Method of controlling ion energy distribution using a pulse generator

Patent metadata

Field	Value
Publication number	US-11284500-B2
Application number	US-202016933311-A
Country	US
Kind code	B2
Filing date	Jul 20, 2020
Priority date	May 10, 2018
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

Embodiments of this disclosure describe an electrode biasing scheme that enables maintaining a nearly constant sheath voltage and thus creating a mono-energetic IEDF at the surface of the substrate that consequently enables a precise control over the shape of IEDF and the profile of the features formed in the surface of the substrate.

First claim

The invention claimed is:

1. A pulsed DC biasing system, comprising:
a substrate support assembly comprising a biasing electrode and a substrate-supporting surface, wherein the biasing electrode is electrically coupled to a first electrical conductor;
a bias generator that is electrically coupled to a second electrical conductor;
a blocking capacitor electrically coupled between the first electrical conductor and the second electrical conductor;
a blocking resistor electrically coupled to the first electrical conductor at a connection point disposed between the blocking capacitor and the biasing electrode; and
a non-transitory computer readable medium having instructions stored thereon for performing a method of processing a substrate when executed by a processor, the method comprising:
generating a plasma over a surface of a substrate disposed on the substrate-supporting surface;
using the bias generator to establish a pulsed voltage waveform at the biasing electrode through the blocking capacitor; and
chucking the substrate to the substrate support assembly by delivering a chucking voltage from a high-voltage module to the biasing electrode through the first electrical conductor.

2. The pulsed DC biasing system of claim 1 , wherein the biasing electrode is spaced apart from the substrate-supporting surface by a layer of dielectric material.

3. The pulsed DC biasing system of claim 1 , wherein the blocking capacitor has a capacitance of between about 40 nF and about 80 nF.

4. The pulsed DC biasing system of claim 1 , wherein the high-voltage module is electrically coupled to the first electrical conductor at a connection point disposed between the biasing electrode and the blocking capacitor.

5. The pulsed DC biasing system of claim 4 , wherein the high-voltage module is disposed between the blocking resistor and ground.

6. The pulsed DC biasing system of claim 5 , wherein the blocking resistor has a resistance of more than about 1 MOhm.

7. The pulsed DC biasing system of claim 6 , wherein the high-voltage module is configured to apply a voltage to the first electrical conductor relative to the ground.

8. The pulsed DC biasing system of claim 1 , wherein
the high-voltage module is electrically coupled to a first end of the first electrical conductor,
the biasing electrode is coupled to a second end of the first electrical conductor,
the blocking capacitor is disposed between the first end of the first electrical conductor and the bias generator, and
the blocking resistor is disposed between the first end of the first electrical conductor and the bias generator.

9. The pulsed DC biasing system of claim 1 , wherein
the pulsed voltage waveform comprises a series of repeating cycles,
a waveform within each cycle of the series of repeating cycles has a first portion that occurs during a first time interval and a second portion that occurs during a second time interval, and
a positive voltage pulse is only present during the first time interval.

10. The pulsed DC biasing system of claim 9 , wherein
the pulsed voltage waveform is substantially constant during at least a portion of the second time interval, and
the second time interval is longer than the first time interval.

11. The pulsed DC biasing system of claim 10 , wherein
the high-voltage module is electrically coupled between ground and the first electrical conductor, and
the chucking voltage is applied to the first electrical conductor relative to the ground.

12. A pulsed DC biasing system, comprising:
a substrate support assembly comprising a biasing electrode and a substrate-supporting surface;
a bias generator electrically coupled to the biasing electrode;
a blocking capacitor electrically coupled to the biasing electrode using a first electrical conductor, wherein the blocking capacitor is electrically coupled between the bias generator and the biasing electrode;
a blocking resistor electrically coupled to the first electrical conductor at a connection point disposed between the blocking capacitor and the biasing electrode; and
a non-transitory computer readable medium having instructions stored thereon for performing a method of processing a substrate when executed by a processor, the method comprising:
generating a plasma over a surface of a substrate disposed on the substrate-supporting surface,
using the bias generator to establish a pulsed voltage waveform at the biasing electrode through the blocking capacitor; and
chucking the substrate to the substrate support assembly by delivering a chucking voltage from a high-voltage module to the biasing electrode through the first electrical conductor.

13. The pulsed DC biasing system of claim 12 , wherein
the pulsed voltage waveform comprises a series of repeating cycles,
a waveform within each cycle of the series of repeating cycles has a first portion that occurs during a first time interval and a second portion that occurs during a second time interval, and
a positive voltage pulse is only present during the first time interval.

14. The pulsed DC biasing system of claim 13 , further comprising a second electrical conductor coupled to the bias generator, wherein
the blocking capacitor is coupled between the first electrical conductor and the second electrical conductor.

15. The pulsed DC biasing system of claim 14 , wherein the high-voltage module is disposed between the blocking resistor and ground.

16. The pulsed DC biasing system of claim 14 , wherein
the substrate is spaced apart from the biasing electrode by a layer of dielectric material of the substrate support assembly.

17. A non-transitory computer readable medium having instructions stored thereon for performing a method of processing a substrate when executed by a processor, the method comprising:
generating a plasma over a surface of a substrate disposed on a substrate-supporting surface of a substrate support assembly comprising a biasing electrode and a substrate-supporting surface, wherein the biasing electrode is electrically coupled to a first electrical conductor;
using a bias generator to establish a pulsed voltage waveform at the biasing electrode through a blocking capacitor, wherein the bias generator is electrically coupled to a second electrical conductor; and
chucking the substrate to the substrate support assembly by delivering a chucking voltage from a high-voltage module to the biasing electrode through the first electrical conductor, wherein
the blocking capacitor is coupled between the first electrical conductor and the second electrical conductor, and
a blocking resistor is electrically coupled to the first electrical conductor at a connection point disposed between the blocking capacitor and the biasing electrode.

18. The computer readable medium of claim 17 , wherein
the pulsed voltage waveform comprises a series of repeating cycles, and
a waveform within each cycle of the series of repeating cycles has a first portion that occurs during a first time interval and a second portion that occurs during a second time interval.

19. The computer readable medium of claim 18 , wherein a positive voltage pulse is only present during the first time interval.

20. The computer readable medium of claim 19 , wherein the substrate is spaced apart from the biasing electrode by a layer of dielectric material of the substrate support assembly.

Assignees

• Applied Materials Inc

Inventors

• Dorf Leonid
• Luere Olivier
• Dhindsa Rajinder
• Rogers James
• Srinivasan Sunil
• Mishra Anurag Kumar

Classifications

• H10P72/0421

  for drying etching · CPC title

• H05H2242/20

  Power circuits · CPC title

• H01J37/32146 Primary

  Amplitude modulation, includes pulsing · CPC title

• H01J37/3467

  Pulsed operation, e.g. HIPIMS · CPC title

• H01J2237/3348

  control of ion bombardment energy · CPC title