FET device insensitive to noise from drive path

Patent metadata

Field	Value
Publication number	US-11282959-B2
Application number	US-202016931929-A
Country	US
Kind code	B2
Filing date	Jul 17, 2020
Priority date	Jul 17, 2020
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

A FET device has a substrate, a plurality of repetitive source stripes, a first layout of drain stripe having a first drift region and a first drain region, a second layout of drain stripe having a second drift region and a second drain region, a first drain contactor contacted with the first drain region and connected to a drain terminal, a second drain contactor contacted with the second drain region and connected to a first gate terminal, a source contactor contacted with a source region in each of the plurality of repetitive source stripes and connected to a source terminal, a first gate region positioned between the source region and the first drain region and connected to the first gate terminal, and a second gate region positioned between the source region and the second drain region and connected to a second gate terminal.

First claim

We claim:

1. A FET device, having a drain terminal, a source terminal, a first gate terminal, and a second gate terminal, the FET device comprising:
a substrate of a first conductivity type;
a first layout of drain stripe, having a first drift region of a second conductivity type, and a first drain region of the second conductivity type;
a second layout of drain stripe, having a second drift region of the second conductivity type, and a second drain region of the second conductivity type;
a plurality of repetitive source stripes, each of the plurality of repetitive source stripes having a source region of the second conductivity type, and a body region of the first conductivity type, at least one of the plurality of repetitive source stripes is located between the first layout of drain stripe and the second layout of drain stripe;
a first drain contactor, positioned above the substrate and contacted with the first drain region, the first drain contactor is connected to the drain terminal of the FET device;
a second drain contactor, positioned above the substrate and contacted with the second drain region, the second drain contactor is connected to the first gate terminal of the FET device;
a source contactor, positioned above the substrate and contacted with the source region and the body region, the source contactor is connected to the source terminal of the FET device;
a first gate region, positioned above the substrate, and positioned between the source region and the first drain region, the first gate region is connected to the first gate terminal of the FET device; and
a second gate region, positioned above the substrate, and positioned between the source region and the second drain region, the second gate region is connected to the second gate terminal of the FET device.

2. The FET device of claim 1 , wherein a layout size of the second layout of drain stripe is smaller than a layout size of the first layout of drain stripe.

3. The FET device of claim 1 , wherein a lateral width of the first gate region is larger than a lateral width of the second gate region.

4. The FET device of claim 1 , wherein a space from an edge of the first drain region to an edge of the first gate region is larger than a space from an edge of the second drain region to an edge of the second gate region.

5. The FET device of claim 1 , further comprising a plurality of power FET cells and a plurality of pull down FET cells, each of the plurality of power FET cells is formed by the first drain region, the source region, the body region, and the first gate region, and each of the plurality of pull down FET cells is formed by the second drain region, the source region, the body region, and the second gate region.

6. The FET device of claim 1 , further comprising a buried layer of the first conductivity type formed in the substrate, wherein the first layout of drain stripe, the second layout of drain stripe, and the plurality of repetitive source stripes are positioned above the buried layer.

7. The FET device of claim 1 , wherein the first gate region comprises a first gate oxide and a first gate polysilicon, and the second gate region comprises a second gate oxide and a second gate polysilicon.

8. The FET device of claim 7 , wherein the source region further comprises a first portion and a second portion respectively distributed on both sides of the body region, the first gate oxide is configured to touch the first portion of the source region and the second gate oxide is configured to touch the second portion of the source region.

9. A FET device, comprising:
a substrate of a first conductivity type;
a first drain region of a second conductivity type;
a first drain contactor, positioned above the substrate and contacted with the first drain region, the first drain contactor is connected to a drain terminal of the FET device;
a second drain region of the second conductivity type;
a second drain contactor, positioned above the substrate and contacted with the second drain region, the second drain contactor is connected to a first gate terminal of the FET device;
a source region of the second conductivity type, the source region is between the first drain region and the second drain region, the source region contacts a first gate region and a second gate region;
a source contactor, positioned above the substrate and contacted with the source region, the source contactor is connected to a source terminal of the FET device;
the first gate region, positioned between the source region and the first drain region, and the first gate region is connected to the first gate terminal of the FET device; and
the second gate region, positioned between the source region and the second drain region, and the second gate region is connected to a second gate terminal of the FET device.

10. The FET device of claim 9 , wherein a lateral width of the first gate region is larger than a lateral width of the second gate region.

11. The FET device of claim 9 , wherein a space from an edge of the first drain region to an edge of the first gate region is larger than a space from an edge of the second drain region to an edge of the second gate region.

12. The FET device of claim 9 , wherein the first gate region comprises a first gate oxide and a first gate polysilicon, and the second gate region comprises a second gate oxide and a second gate polysilicon.

13. The FET device of claim 12 , wherein the source region comprises a first portion and a second portion respectively distributed on both sides of a body region, wherein the first gate oxide is configured to touch the first portion of the source region and the second gate oxide is configured to touch the second portion of the source region.

14. The FET device of claim 9 , wherein a power FET cell is formed by the first drain region, the source region and the first gate region, and a pull down FET cell is formed by the second drain region, the source region, and the second gate region.

15. The FET device of claim 14 , wherein a layout size of the pull down FET cell is smaller than a layout size of the power FET cell.

16. The FET device of claim 14 , further comprising a plurality of repetitive power FET cells, and a plurality of repetitive pull down FET cells, wherein a quantity of the plurality of repetitive power FET cells is more than a quantity of the plurality of repetitive pull down FET cells.

Assignees

• Monolithic Power Systems Inc

Inventors

• Braun Eric
• Nguyen James

Classifications

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/158

  Dispositions · CPC title

• H10D62/154

  Dispositions · CPC title

• H10D30/664

  Inverted VDMOS transistors, i.e. source-down VDMOS transistors · CPC title

• H10D30/663

  having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS · CPC title