Semiconductor device reducing parasitic loop inductance of system

Patent metadata

Field	Value
Publication number	US-10083930-B2
Application number	US-201715411899-A
Country	US
Kind code	B2
Filing date	Jan 20, 2017
Priority date	Jan 22, 2016
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A semiconductor device reducing parasitic loop inductance of system for the switching converter. The semiconductor device has an input voltage pin, a ground reference pin, a switching pin, and a semiconductor die, wherein the semiconductor die comprises a high-side power switch and a low-side power switch and a metal connection. The metal connection directly connects the high-side power switch and the first terminal of the low-side power switch, and is along and proximity to an edge of the semiconductor device to which the input voltage pin is distributed.

First claim

What is claimed is:

1. A semiconductor device used with a switching converter, comprising:
an input voltage pin configured to receive an input voltage of the switching converter;
a ground reference pin coupled to a ground reference of the switching converter;
a switching pin;

a high-side power switch having a first terminal coupled to the input voltage pin and a second terminal coupled to the switching pin via lead frames;
a low-side power switch having a first terminal coupled to the switching pin and a second terminal coupled to the ground reference pin via lead frames; and
a metal connection configured to connect the second terminal of the high-side power switch and the first terminal of the low-side power switch, wherein the metal connection is located on a semiconductor die integrating the high-side power switch and the low-side power switch, and is along and proximity to an edge of the semiconductor device to which the input voltage pin is distributed.

2. The semiconductor device of claim 1 , wherein the metal connection is located on a RDL (Re-Distribution Layer) of the semiconductor die.

3. The semiconductor device of claim 1 , wherein the metal connection is located on any metal layer of the semiconductor die.

4. The semiconductor device of claim 1 , wherein the input voltage pin and the ground reference pin are distributed to the same edge of the semiconductor device.

5. The semiconductor device of claim 1 , used with an input capacitor of the switching converter, wherein the input capacitor is proximity to the same edge of the semiconductor device with the metal connection, and is attached to a same PCB with the semiconductor device.

6. A hardware circuit, comprising:
a semiconductor device used with a switching converter, wherein the semiconductor device comprises:
an input voltage pin configured to receive an input voltage of the switching converter;
a ground reference pin coupled to an ground reference of the switching converter;
a switching pin;
a high-side power switch having a first terminal coupled to the input voltage pin and a second terminal coupled to the switching pin via lead frames;
a low-side power switch having a first terminal coupled to the switching pin and a second terminal coupled to the ground reference pin via lead frames; and
a metal connection configured to connect the second terminal of the high-side power switch and the first terminal of the low-side power switch, wherein the metal connection is located on a semiconductor die integrating the high-side power switch and the low-side power switch, and is along and proximity to an edge of the semiconductor device to which the input voltage pin is distributed; and

a PCB (Printed Circuit Board) having an input voltage metal layer, a ground reference metal layer, and a switching node metal layer.

7. The hardware circuit of claim 6 , further comprising an input capacitor being proximity to the same edge of the semiconductor device with the metal connection, wherein the input capacitor has a first terminal coupled with the input voltage pin of the semiconductor device via the input voltage metal layer and a second terminal coupled to the ground reference pin of the semiconductor device via the ground reference metal layer, and is attached to the same PCB with the semiconductor device.

8. The hardware circuit of claim 6 , wherein the metal connection is located on a RDL of the semiconductor die.

9. The hardware circuit of claim 6 , wherein the metal connection is located on any metal layer of the semiconductor die.

10. The hardware circuit of claim 6 , wherein the input voltage pin and the ground reference pin are distributed to the same edge of the semiconductor device.

11. A hardware circuit, comprising:
a semiconductor device used with a switching converter, wherein the semiconductor device comprises:
an input voltage pin configured to receive an input voltage of the switching converter;
a ground reference pin coupled to an ground reference of the switching converter;
a switching pin;
a high-side power switch having a first terminal coupled to the input voltage pin and a second terminal coupled to the switching pin via lead frames;
a low-side power switch having a first terminal coupled to the switching pin and a second terminal coupled to the ground reference pin via lead frames; and
a metal connection configured to connect the second terminal of the high-side power switch and the first terminal of the low-side power switch, wherein the metal connection is located on a semiconductor die integrating the high-side power switch and the low-side power switch, and is along and proximity to an edge of the semiconductor device;

a PCB (Printed Circuit Board) having an input voltage metal layer, a ground reference metal layer, and a switching node metal layer; and
an input capacitor having a first terminal coupled with the input voltage pin of the semiconductor device via the input voltage metal layer and a second terminal coupled to the ground reference pin of the semiconductor device via the ground reference metal layer, wherein the input capacitor is attached to the same PCB with the semiconductor device;
wherein, the edge of the semiconductor device, which the metal connection is along and proximity to, is proximity to the input capacitor.

12. The hardware circuit of claim 11 , wherein the metal connection is located on a RDL of the semiconductor die.

13. The hardware circuit of claim 11 , wherein the metal connection is located on any metal layer of the semiconductor die.

Assignees

• Monolithic Power Systems Inc

Inventors

• Wang Huaifeng
• Braun Eric
• Jiang Hunt Hang
• Yu Francis

Classifications

• H10W70/475

  Capacitors in combination with leadframes · CPC title

• H10W90/811 Primary

  Multiple chips on leadframes · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W72/07336

  Soldering or alloying · CPC title

• H10W72/352

  comprising metals or metalloids, e.g. solders · CPC title