CMOS transistor, semiconductor device including the transistor, and semiconductor module including the device

Patent metadata

Field	Value
Publication number	US-9287199-B2
Application number	US-97296110-A
Country	US
Kind code	B2
Filing date	Dec 20, 2010
Priority date	Jan 25, 2010
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate doped with a first conductivity type impurity;
an insulating layer formed on the semiconductor substrate, the insulating layer having a trench therein to expose a portion of the substrate;
a gate insulating layer formed on the portion of the substrate in the trench; and
a multilayer gate electrode formed in the trench comprising:
a metal nitride layer formed on the gate insulating layer;
a metal containing layer of a concave shape formed on the metal nitride layer, the metal containing layer having outer sidewalls and inner sidewalls;
a concave shape conductive layer formed on the inner sidewalls of the metal containing layer; and
a filling metal formed on the concave shape conductive layer to fill a portion of the trench, wherein the metal nitride layer does not extend along the outer sidewalls of the metal containing layer; and
a capping layer pattern formed in the trench to cover at least an upper surface of the filling metal,
wherein the capping layer comprises a material having an etching rate different from that of the insulating layer, and
wherein the concave shape conductive layer is not formed on an upper surface of the metal containing layer.

2. The semiconductor device of claim 1 , wherein the outer sidewalls of the metal containing layer contacts the insulating layer.

3. The semiconductor device of claim 1 , wherein the metal nitride layer comprises a binary-based metal nitride or a ternary based metal nitride.

4. The semiconductor device of claim 3 , wherein the metal containing layer comprises a metal aluminum nitride.

5. The semiconductor device of claim 4 , wherein the metal aluminum nitride comprises HfAlN, TaAlN, or TiAlN.

6. The semiconductor device of claim 1 , where a upper surface of the filling metal and a upper surface of the concave shape conductive layer are coplanar.

7. The semiconductor device of claim 1 , wherein the gate insulating layer comprises hafnium-based oxide.

8. The semiconductor device of claim 1 , wherein an upper surface of the capping layer is coplanar with an upper surface of the insulating layer.

9. A semiconductor device comprising:
a semiconductor substrate including a first region and a second region, the first region doped with a first conductivity type impurity and the second region doped with a second conductivity type impurity;
an insulating layer formed on the semiconductor substrate, the insulating layer having a first trench therein to expose a portion of the substrate;
a first gate insulating layer formed on the portion of the substrate in the first trench;
a first multilayer gate electrode formed in the first trench comprising:
a first metal nitride layer formed on the first gate insulating layer;
a metal containing layer of a concave shape formed on the first metal nitride layer, the metal containing layer having outer sidewalls and inner sidewalls;
a first concave shape conductive layer formed on the inner sidewalls of the metal containing layer; and
a first filling metal formed on the first concave shape conductive layer to fill a portion of the first trench, wherein the first metal nitride layer does not extend along the outer sidewalls of the metal containing layer,
the insulating layer further comprising a second trench to expose another portion of the substrate;

a second gate insulating layer formed on the another portion of the substrate in the second trench;
a second multilayer gate electrode formed in the second trench comprising:
a second metal nitride layer formed on the second gate insulating layer;
a second concave shape conductive layer formed on sidewalls of the second trench; and
a second filling metal formed on the second concave shape conductive layer to fill a portion of the second trench;

a first capping layer pattern formed in the first trench to cover at least an upper surface of the first filling metal, and
a second capping layer pattern formed in the second trench to cover at least an upper surface of the second filling metal,
wherein the first and second capping layers comprise a material having an etching rate different from that of the insulating layer.

10. The semiconductor device of claim 9 , wherein the outer sidewalls of the metal containing layer contacts the insulating layer.

11. The semiconductor device of claim 9 , wherein the first metal nitride layer comprises a binary-based metal nitride or a ternary based metal nitride, and the second metal nitride layer comprises a binary-based metal nitride or a ternary based metal nitride.

12. The semiconductor device of claim 9 , wherein the metal containing layer comprises a ternary-based metal nitride.

13. The semiconductor device of claim 12 , wherein the ternary-based metal nitride comprises HfAlN, HfSiN, TaAlN, TiAlN, or TiTiN.

14. The semiconductor device of claim 9 , wherein an upper surface of the metal containing layer and an upper surface of the first concave shape conductive layer are coplanar.

15. The semiconductor device of claim 9 , wherein the first gate insulating layer and the second gate insulating layer comprise hafnium-based oxide.

16. The semiconductor device of claim 9 , wherein the first conductive type impurity comprises N-type impurity and the second conductive type impurity comprises P-type impurity.

17. The semiconductor device of claim 9 , wherein the first conductive type impurity comprises P-type impurity and the second conductive type impurity comprises N-type impurity.

18. The semiconductor device of claim 9 , wherein an upper surface of the first capping layer is coplanar with an upper surface of the insulating layer.

19. The semiconductor device of claim 9 , wherein upper surfaces of the first and second capping layers are coplanar with an upper surface of the insulating layer.

20. A semiconductor device comprising:
a semiconductor substrate doped with a first conductivity type impurity;
an insulating layer formed on the semiconductor substrate, the insulating layer having a trench therein to expose a portion of the substrate;
a gate insulating layer formed on the portion of the substrate in the trench; and
a multilayer gate electrode formed in the trench comprising:
a metal nitride layer formed on the gate insulating layer;
a metal containing layer of a concave shape formed on the metal nitride layer, the metal containing layer having outer sidewalls and inner sidewalls;
a concave shape conductive layer formed on the inner sidewalls of the metal containing layer; and
a filling metal formed on the concave shape conductive layer to fill a portion of the trench,

wherein the metal nitride layer does not extend along the outer sidewalls of the metal containing layer; and
a capping layer pattern formed in the trench to cover an upper surface of the filling metal and at least an upper surface of the concave shape conductive layer,
wherein the capping layer comprises a material having an etching rate different from that of the insulating layer.

21. The semiconductor device of claim 20 , wherein the outer sidewalls of the metal containing layer contacts the insulating layer.

22. The semiconductor device of claim 21 , wherein the metal nitride layer comprises a binary-based metal nitride or a ternary based metal nitride.

23. The semiconductor device of claim 22 , wherein the metal containing layer comprises a ternary-based metal nitride.

24

Assignees

• Lee Hye-Lan
• Park Hong-Bae
• Hyun Sang-Jin
• Shin Yu-Gyun
• Hong Sug-Hun
• Na Hoon-Joo
• Hong Hyung-Seok
• Samsung Electronics Co Ltd

Inventors

• Lee Hye-Lan
• Park Hong-Bae
• Hyun Sang-Jin
• Shin Yu-Gyun
• Hong Sug-Hun
• Na Hoon-Joo
• Hong Hyung-Seok

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/217

  of only conductor-insulator-semiconductor capacitors · CPC title

• H10D84/212

  of only capacitors · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title