Semiconductor device and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-2017200738-A1
Application number	US-201715403307-A
Country	US
Kind code	A1
Filing date	Jan 11, 2017
Priority date	Jan 11, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.

First claim

1 . A semiconductor device, comprising:
a substrate including a first region and a second region; a first wire pattern provided on the first region of the substrate and spaced apart from the substrate; a second wire pattern provided on the second region of the substrate and spaced apart from the substrate; a first gate insulating film surrounding a perimeter of the first wire pattern; a second gate insulating film surrounding a perimeter of the second wire pattern; a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein; a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern; a first gate spacer on a sidewall of the first gate electrode; and a second gate spacer on a sidewall of the second gate electrode.

2 . The semiconductor device of claim 1 , wherein the first gate spacer defines a first trench, and
the first gate electrode includes a first lower gate electrode surrounding the first gate insulating film and extending along a sidewall of the first trench, and a first upper gate electrode provided on the first lower gate electrode and filling the first trench.

3 . The semiconductor device of claim 2 , wherein the first metal oxide film is positioned in a boundary between the first lower gate electrode and the first upper gate electrode.

4 . The semiconductor device of claim 2 , wherein the first metal oxide film is positioned inside the first lower gate electrode, and
the first metal oxide film is spaced apart from the first upper gate electrode and the first gate insulating film.

5 . The semiconductor device of claim 2 , wherein the first metal oxide film includes a first upper metal oxide film and a first lower metal oxide film that are spaced apart from each other, and
the first lower metal oxide film is positioned in a boundary between the first lower gate electrode and the first gate insulating film.

6 . The semiconductor device of claim 1 , wherein the second gate spacer defines a second trench, and
the second gate electrode includes a second lower gate electrode surrounding the second gate insulating film and extending along a sidewall of the second trench, and a second upper gate electrode on the second lower gate electrode, and the second gate electrode does not include a metal oxide film positioned inside the second gate electrode.

7 . The semiconductor device of claim 1 , wherein the second gate spacer defines a second trench, and
the second gate electrode includes a second lower gate electrode surrounding the second gate insulating film and extending along a sidewall of the second trench, and a second upper gate electrode on the second lower gate electrode, and the second gate electrode further includes a second metal oxide film.

8 . The semiconductor device of claim 7 , wherein the second metal oxide film is positioned in a boundary between the second lower gate electrode and the second upper gate electrode.

9 . The semiconductor device of claim 7 , wherein the second metal oxide film is positioned inside the second lower gate electrode, and
the second metal oxide film is spaced apart from the second upper gate electrode and the second gate insulating film.

10 . The semiconductor device of claim 1 , wherein the first gate insulating film comprises an upper portion and a lower portion,
the first gate insulating film includes a metal oxide, and an oxygen-to-metal ratio of the upper portion of the first gate insulating film is different from the oxygen-to-metal ratio of the lower portion of the first gate insulating film.

11 . A semiconductor device, comprising:
a first wire pattern provided on a substrate and spaced apart from the substrate; a second wire pattern provided on the first wire pattern and spaced apart from the first wire pattern; a gate spacer provided on the substrate, the gate spacer being disposed on both sides of the first wire pattern and the second wire pattern, and defining a trench; a gate insulating film surrounding perimeters of the first wire pattern and the second wire pattern and extending along a sidewall of the trench; a lower gate electrode provided on the gate insulating film and surrounding the first wire pattern and the second wire pattern; a metal oxide film provided on the gate insulating film and extending along at least a portion of a profile of the gate insulating film; and an upper gate electrode provided on the lower gate electrode and the metal oxide film and filling the trench.

12 . The semiconductor device of claim 11 , wherein the lower gate electrode surrounding the first wire pattern, and the lower gate electrode surrounding the second wire pattern are spaced apart from each other.

13 . The semiconductor device of claim 12 , wherein the metal oxide film extends along an entire profile of the gate insulating film.

14 . The semiconductor device of claim 12 , wherein the upper gate electrode is interposed between the first wire pattern and the second wire pattern.

15 . The semiconductor device of claim 12 , further comprising an air gap interposed between the first wire pattern and the second wire pattern.

16 . The semiconductor device of claim 15 , wherein the upper gate electrode is not interposed between the first wire pattern and the second wire pattern.

17 . The semiconductor device of claim 15 , wherein the air gap is defined by the metal oxide film and the upper gate electrode.

18 . The semiconductor device of claim 11 , wherein the lower gate electrode surrounds the first wire pattern and the second wire pattern, and
the upper gate electrode is not interposed between the first wire pattern and the second wire pattern.

19 . The semiconductor device of claim 18 , wherein the metal oxide film extends along an entire profile of the gate insulating film.

20 . The semiconductor device of claim 18 , wherein the metal oxide film is positioned at a boundary between the lower gate electrode and the upper gate electrode.

21 - 40 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Bo Soon
• Kim Hyun Ji
• Lee Jeong Yun
• Park Gi Gwan
• Park Sang Duk
• Oh Young Mook
• Lee Yong Seok

Classifications

• H01L29/4908

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L27/1211

  Electricity · mapped topic

• H01L27/1203 Primary

  Electricity · mapped topic

• H01L21/845

  Electricity · mapped topic