Integrated fan-out package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11282810-B2
Application number	US-202016923115-A
Country	US
Kind code	B2
Filing date	Jul 8, 2020
Priority date	May 17, 2018
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

First claim

What is claimed is:

1. A method of manufacturing an integrated fan-out (InFO) package, comprising:
forming a package array;
sequentially stacking a core layer and a dielectric layer over the package array, wherein the core layer comprises a plurality of cavities; and
forming a plurality of first conductive patches on the dielectric layer above the plurality of cavities.

2. The method according to claim 1 , further comprising:
singulating the package array, the dielectric layer, and the core layer.

3. The method according to claim 1 , wherein the step of forming the package array comprises:
providing a first redistribution structure;
forming a plurality of through interlayer vias (TIV) and a plurality of dies over the first redistribution structure;
forming an encapsulant encapsulating the plurality of dies and the plurality of TIVs;
forming a second redistribution structure over the plurality of dies, the plurality of TIVs, and the encapsulant; and
forming an insulating layer over the first redistribution structure opposite to the plurality of dies.

4. The method according to claim 3 , wherein the step of forming the package array further comprises:
forming a plurality of second conductive patches over the insulating layer, wherein the plurality of second conductive patches are located inside of the plurality of cavities of the core layer.

5. The method according to claim 1 , further comprising:
forming a vent in the dielectric layer.

6. The method according to claim 5 , wherein a vertical projection of the vent onto the package array is overlapped with a vertical projection of one of the plurality of cavities onto the package array.

7. The method according to claim 1 , further comprising:
forming a vent in the core layer.

8. A method of manufacturing an integrated fan-out (InFO) package, comprising:
forming a package array;
placing a plurality of core patterns on the package array, wherein each of the plurality of core patterns comprises a plurality of cavities, and the plurality of core patterns exposes at least a portion of the package array;
forming a dielectric layer on the plurality of core patterns to cover the plurality of cavities; and
forming a plurality of first conductive patches on the dielectric layer, wherein the plurality of first conductive patches are arranged corresponding to the plurality of cavities.

9. The method according to claim 8 , wherein the dielectric layer comprises a plurality of discontinuous segments, and each discontinuous segment is formed on the corresponding core pattern such that sidewalls of each discontinuous segment are substantially aligned with sidewalls of the corresponding core pattern.

10. The method according to claim 8 , further comprising:
singulating the package array.

11. The method according to claim 8 , wherein the plurality of cavities of the plurality of core patterns are formed by a punching process or a photolithography process.

12. The method according to claim 8 , wherein the plurality of core patterns are placed on the package array through a pick-and-place process.

13. The method according to claim 8 , wherein the step of forming the package array comprises:
providing a carrier;
forming a first redistribution structure over the carrier;
forming a plurality of through interlayer vias (TIV) and a plurality of dies over the first redistribution structure;
forming an encapsulant encapsulating the plurality of dies and the plurality of TIVs;
forming a second redistribution structure over the plurality of dies, the plurality of TIVs, and the encapsulant; and
forming an insulating layer over the first redistribution structure opposite to the plurality of dies.

14. The method according to claim 13 , wherein the step of forming the package array further comprises:
forming a plurality of second conductive patches over the insulating layer, wherein the plurality of second conductive patches are located inside of the plurality of cavities of the plurality of core patterns.

15. The method according to claim 8 , further comprising:
forming a vent in each of the plurality of core patterns; and
forming a vent in the dielectric layer.

16. An integrated fan-out (InFO) package, comprising:
a package structure;
a core layer over the package structure, wherein the core layer comprises a plurality of cavities penetrating through the core layer;
a dielectric layer over the core layer; and
a plurality of first conductive patches over the dielectric layer, wherein the plurality of first conductive patches are arranged corresponding to the plurality of cavities.

17. The InFO package according to claim 16 , further comprising an adhesive layer sandwiched between the dielectric layer and the plurality of first conductive patches.

18. The InFO package according to claim 16 , wherein the package structure comprises:
a first redistribution structure;
a plurality of through interlayer vias (TIV) and a die over the first redistribution structure;
an encapsulant encapsulating the die and the plurality of TIVs;
a second redistribution structure over the die, the plurality of TIVs, and the encapsulant; and
an insulating layer over the first redistribution structure opposite to the die.

19. The InFO package according to claim 18 , wherein the package structure further comprises:
a plurality of second conductive patches over the insulating layer, wherein the plurality of second conductive patches are located inside of the plurality of cavities of the core layer.

20. The InFO package according to claim 16 , wherein the dielectric layer comprises a vent.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wan Albert
• Hsieh Ching-Hua
• Tsai Chung-Hao
• Wang Chuei-Tang
• Shih Chao-Wen
• Pu Han-Ping
• Hwang Chien-Ling
• Lee Pei-Hsuan
• Tang Tzu-Chun
• Chiu Yu-Ting
• Kuo Jui-Chang

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W44/248

  for antennas · CPC title