Embedded bonded assembly and method for making the same

Patent metadata

Field	Value
Publication number	US-11276705-B2
Application number	US-201916552089-A
Country	US
Kind code	B2
Filing date	Aug 27, 2019
Priority date	Aug 27, 2019
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.

First claim

The invention claimed is:

1. A semiconductor structure, comprising:
a first semiconductor die containing a recess; and
a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die;
wherein:
the first semiconductor die comprises a first substrate and a first device overlying the first substrate, the first semiconductor die having a first topmost surface overlying the first device and a first recessed surface in the recess;
the second semiconductor die comprises a second substrate and a second device overlying the second substrate, the second substrate having a bottom surface facing away from the second device, and the second semiconductor die having a second topmost surface overlying the second device;
the second topmost surface of the second semiconductor die is bonded to the first recessed surface of the first semiconductor die;
the bottom surface of the second substrate is coplanar with the first topmost surface; and
backside metal interconnection structures and backside dielectric material layer are located over the bottom surface of the second substrate and over the first topmost surface.

2. The semiconductor structure of claim 1 , wherein:
the first device comprises a three-dimensional memory device located over the first substrate;
the first topmost surface comprises a topmost memory die surface located at a first height from a top surface of the first substrate in a first area;
the first recessed surface comprises a recessed memory die surface located at a second height from the top surface of the first substrate in at least one second area containing the recess, the second height being less than the first height;
the second device comprises a logic circuit unit disposed within the recess;
the logic circuit unit comprises the second substrate, a logic circuit, and first metal interconnect structures; and
the first metal interconnect structures are more proximal to the first substrate than the second substrate is to the first substrate.

3. The semiconductor structure of claim 2 , wherein the backside dielectric material layer is in direct contact with the topmost memory die surface.

4. The semiconductor structure of claim 2 , further comprising through-substrate via structures vertically extending through the second substrate and providing electrical connection between the first metal interconnect structures and the backside metal interconnection structures.

5. The semiconductor structure of claim 4 , wherein the second substrate is laterally surrounded by, and is contacted by on at least two sides by, a portion of the three-dimensional memory device located within the first area.

6. The semiconductor structure of claim 5 , wherein the logic circuit unit is located in the recess and is laterally spaced apart from another logic circuit unit by a portion of the three-dimensional memory device located within the first area.

7. The semiconductor structure of claim 2 , wherein:
the three-dimensional memory device comprises first bonding pads having a respective top surface adjoined to the at least one recessed memory die surface; and
the logic circuit unit comprises second bonding pads bonded to the respective first bonding pads.

8. The semiconductor structure of claim 2 , wherein the three-dimensional memory device comprises a three-dimensional NAND memory device which includes:
at least one alternating stack of insulating layers and electrically conductive layers;
memory openings vertically extending through the at least one alternating stack; and
memory opening fill structures located within a respective one of the memory openings, wherein each of the memory opening fill structures comprises a vertical semiconductor channel and a memory film.

9. The semiconductor structure of claim 8 , wherein:
the at least one alternating stack comprises stepped surfaces that continuously extend across the first area and the second area;
a first retro-stepped dielectric material portion is located on a first portion of the stepped surfaces located in the second area;
a second retro-stepped dielectric material portion is located on a second portion of the stepped surfaces and located in the first area; and
contact via structures vertically extend through the first retro-stepped dielectric material portion or the second retro-stepped dielectric material portion and contact a respective one of the electrically conductive layers.

10. The semiconductor structure of claim 9 , wherein the contact via structures comprise:
first contact via structures extending through the first retro-stepped dielectric material portion and contacting a first subset of the electrically conductive layers; and
second contact via structures extending through the second retro-stepped dielectric material portion and contacting a second subset of the electrically conductive layers,
wherein:
the second subset of the electrically conductive layers overlies the first subset of the electrically conductive layers;
top surfaces of the first contact via structures are located underneath a horizontal plane including the recessed memory die surface; and
top surfaces of the second contact via structures are located above the horizontal plane including the recessed memory die surface.

Assignees

• Sandisk Technologies Llc

Inventors

• Wu Chen
• Rabkin Peter
• Chen Yangyin
• Higashitani Masaaki

Classifications

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W90/722

  between stacked chips · CPC title