Integrated circuits and methods for forming thin film crystal layers

US11276644B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11276644-B2
Application numberUS-201816221798-A
CountryUS
Kind codeB2
Filing dateDec 17, 2018
Priority dateDec 17, 2018
Publication dateMar 15, 2022
Grant dateMar 15, 2022

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit comprising: a first electrically conductive structure comprising a first Cu concentration; a diffusion barrier comprising a thin film crystal layer located on the first electrically conductive structure, wherein the thin film crystal layer is a heterojunction thin film crystal layer comprising at least two different thin film crystals; wherein the thin film crystals comprise a transition metal dichalcogenide, a ternary MAX phase carbide, or ternary MAX phase nitride material; and a second electrically conductive structure comprising metal, wherein the second electrically conductive structure comprises greater than 50% copper as a second Cu concentration, wherein the first Cu concentration is less than 20% of the second Cu concentration, wherein the second electrically conductive structure is located on the thin film crystal layer, and wherein the first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. 2. The integrated circuit according to claim 1 , wherein the second electrically conductive structure comprises copper. 3. The integrated circuit according to claim 1 , wherein a thickness of the thin film crystal layer is smaller than 10 nm. 4. The integrated circuit according to claim 1 , wherein the thin film crystal layer comprises less than 20 two-dimensional crystalline monolayers. 5. The integrated circuit according to claim 1 , wherein the thin film crystal layer comprises at least 10% of metal atoms, wherein the metal atoms are Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Rf, Db, Sg, Bh, Hs, Mt, Ds, or Rg. 6. The integrated circuit according to claim 1 , wherein the thin film crystal layer comprises at least 10% of secondary atoms, wherein the secondary atoms are S, Cl, H, O, Se, or Te. 7. The integrated circuit according to claim 1 , wherein the heterojunction thin film crystal layer comprises the ternary MAX phase carbide or ternary MAX phase nitride material as a first thin film crystal layer and the transition metal dichalcogenide layer as a second thin film crystal layer. 8. The integrated circuit according to claim 1 , wherein the second electrically conductive structure is electrically connected to at least one of a source region, a drain region, and a gate of a transistor of the integrated circuit. 9. The integrated circuit according to claim 1 , wherein a contact interface between the thin film crystal layer and a structure adjacent to the thin film crystal layer is voidless.

Assignees

Inventors

Classifications

  • the conductive layers comprising transition metals · CPC title

  • being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

  • using transformation of metal, e.g. oxidation or nitridation · CPC title

  • by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition · CPC title

  • Vias, e.g. via plugs · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11276644B2 cover?
An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first elec…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W20/425. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 15 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).