Memory including a 1R1RW bitcell storage array and methods thereof

Patent metadata

Field	Value
Publication number	US-11276458-B2
Application number	US-202017080242-A
Country	US
Kind code	B2
Filing date	Oct 26, 2020
Priority date	Apr 27, 2018
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

A memory and a signal processing method are provided. The memory includes a latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit. The storage array includes M rows and N columns of bitcells. The latch circuit is configured to receive a first address and a second address. The decoding circuit is configured to: determine a first bitcell based on the first address, and determine a second bitcell based on the second address. The write circuit is configured to: receive data, and write the data into the first bitcell through a first port of the first bitcell. The read circuit is configured to read, through the first port of the first bitcell, data stored in the first bitcell; and is further configured to read, through a second port of the second bitcell, data stored in the second bitcell. Implementing this application can implement 1R1RW.

First claim

What is claimed is:

1. A memory, comprising:
a latch circuit;
a decoding circuit, wherein the latch circuit is connected to the decoding circuit;
a storage array, comprising M rows and N columns of bitcells, wherein each bitcell of the storage array is configured to store 1-bit data, and each bitcell of the storage array comprises a respective first port and a respective second port;
a read circuit, comprising a first sense amplifier and a second sense amplifier, wherein a number of inputs from the storage array to the first sense amplifier is different than a number of inputs from the storage array to the second sense amplifier; and
a write circuit, wherein the storage array is connected to the decoding circuit, the read circuit, and the write circuit; and
wherein:
the latch circuit is configured to receive a first address and a second address;
the decoding circuit is configured to:
determine a first bitcell from the M×N bitcells based on the first address; and
determine a second bitcell from the M×N bitcells based on the second address;

the write circuit is configured to receive data, and write the received data into the first bitcell through a first port of the first bitcell; and
the read circuit is configured to:
read, through the first port of the first bitcell, data stored in the first bitcell; and
read, through a second port of the second bitcell, data stored in the second bitcell.

2. The memory according to claim 1 , wherein in the storage array, and for each integer value of i from 1 to M, each bitcell in an i th row of bitcells is connected to an i th bit line, an i th bit line bar, and an i th read bit line; and
wherein in the storage array, for each integer value of j from 1 to N, each bitcell in a j th column of bitcells is connected to a j th read/write word line and a j th read word line; and
wherein, for each bitcell in the storage array, the bit line connected to the respective bitcell, the bit line bar connected to the respective bitcell, and the read/write word line connected to the respective bitcell form the first port of the respective bitcell, and the read bit line connected to the respective bitcell and the read word line connected to the respective bitcell form the second port of the respective bitcell.

3. The memory according to claim 2 , wherein:
the first bitcell comprises eight MOS transistors M 1 to M 8 , wherein M 1 , M 3 , M 5 , M 6 , M 7 , and M 8 are N-MOS transistors, and M 2 and M 4 are P-MOS transistors;
a source of M 2 and a source of M 4 are connected to a high level, and a source of M 1 and a source of M 3 are connected to a ground level;
a source of M 6 , a gate of M 2 , a gate of M 1 , a drain of M 4 , a drain of M 3 , and a gate of M 7 are connected;
a source of M 5 , a gate of M 4 , a gate of M 3 , a drain of M 2 , and a drain of M 1 are connected;
a gate of M 5 and a gate of M 6 are connected to the read/write word line connected to the first bitcell, a drain of M 5 is connected to the bit line connected to the first bitcell, and a drain of M 6 is connected to the bit line bar connected to the first bitcell;
a gate of M 8 is connected to the read word line connected to the first bitcell, and a drain of M 8 is connected to the read bit line connected to the first bitcell; and
a source of M 8 is connected to a drain of M 7 , and a source of M 7 is connected to the ground level.

4. The memory according to claim 3 , wherein a first input end of the first sense amplifier is connected to each bit line in the storage array, and a second input end of the first sense amplifier is connected to each bit line bar in the storage array; and
wherein an input end of the second sense amplifier is connected to each read bit line in the storage array.

5. The memory according to claim 4 , wherein the second sense amplifier is an asymmetric sense amplifier.

6. The memory according to claim 4 , wherein the read circuit is further configured to:
output the data stored in the first bitcell through an output end of the first sense amplifier after amplifying, using the first sense amplifier, a difference between a voltage received by the first input end and a voltage received by the second input end.

7. The memory according to claim 4 , wherein the read circuit is further configured to:
output the data stored in the second bitcell through an output end of the second sense amplifier after amplifying, by using the second sense amplifier, a voltage received by the input end of the second sense amplifier.

8. The memory according to claim 1 , wherein:
the latch circuit comprises a first address latch circuit and a second address latch circuit, wherein the first address latch circuit is configured to receive the first address, and the second address latch circuit is configured to receive the second address;
the decoding circuit comprises a first decoding circuit and a second decoding circuit, wherein the first decoding circuit is configured to determine the first bitcell from the M×N bitcells based on the first address, and the second decoding circuit is configured to determine the second bitcell from the M×N bitcells based on the second address; and
the first address latch circuit is connected to the first decoding circuit, the second address latch circuit is connected to the second decoding circuit, the first decoding circuit is connected to the storage array through the first port of each bitcell, and the second decoding circuit is connected to the storage array through the second port of each bitcell.

9. The memory according to claim 8 , wherein the first decoding circuit comprises a first row decoder and a first column decoder, wherein the first row decoder is configured to determine, based on the first address, a row in which the first bitcell is located in the M×N bitcells, and the first column decoder is configured to determine, based on the first address, a column in which the first bitcell is located in the M×N bitcells.

10. The memory according to claim 8 , wherein the second decoding circuit comprises a second row decoder and a second column decoder, wherein the second row decoder is configured to determine, based on the second address, a row in which the second bitcell is located in the M×N bitcells, and the second column decoder is configured to determine, based on the second address, a column in which the second bitcell is located in the M×N bitcells.

11. The memory according to claim 1 , wherein:
the read circuit comprises a first read circuit and a second read circuit, wherein the first read circuit is configured to read, through the first port of the first bitcell, data stored in the first bitcell, and the second read circuit is configured to read, through the second port of the second bitcell, data stored in the second bitcell; and
the first read circuit is connected to the storage array through the first port of each bitcell, and the second read circuit is connected to the storage array through the second port of each bitcell.

12. The memory according to claim 1 , wherein:
the memory further comprises a control circuit, and the control circuit is connected to the latch circuit, the decoding circuit, the write circuit, and the read circuit; and
the control circuit is configured to receive a first signal and a second signal, wherein the first signal indicates to the memory to perform a read operation or a write operation through the first port, and the second signal indicates to the memory to perform a read operation through the second port.

13. The memory according to claim 12 , wherein:
the latch circuit is further configured to receive a read/write ena

Assignees

• Huawei Tech Co Ltd

Inventors

• Ji Bingwu
• Zhao Tanfu
• Zhou Yunming
• Fan Min
• Li Zhiyan
• Wang Yunpeng

Classifications

• G11C11/418

  Address circuits · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C8/18

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title