Static random access memory cell and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9761302-B1
Application number	US-201615092613-A
Country	US
Kind code	B1
Filing date	Apr 6, 2016
Priority date	Apr 6, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A SRAM cell includes a first pass-gate device and a second-pass gate device comprising a first conductivity type, a first pull-down device and a second pull-down device comprising the first conductivity type, and a first pull-up device and a second pull-up device comprising a second conductivity type complementary to the first conductivity type. The first pass-gate device and the second pass-gate device respectively include first lightly-doped drains (hereinafter abbreviated as LDDs. The first pull-down device and the second pull-down device respectively include second LDDs. And a dosage of the first LDDs is different from a dosage of the second LDDs.

First claim

What is claimed is:

1. A static random access memory (SRAM) cell comprising:
a first pass-gate device and a second-pass gate device comprising a first conductivity type, and the first pass-gate device and the second pass-gate device respectively comprising a gate layer and first lightly-doped drains (LDDs) formed at two sides of the gate layer, and the first LDDS comprising the first conductivity type;
a first pull-down device and a second pull-down device comprising the first conductivity type, and the first pull-down device and the second pull-down device respectively comprising a gate layer and second LDDs formed at two sides of the gate layer, and the second LDDS comprising the first conductivity type; and
a first pull-up device and a second pull-up device comprising a second conductivity type complementary to the first conductivity type, wherein a dosage of the first LDDs is different from a dosage of the second LDDs, and a threshold voltage of the first pull-down device and the second pull-down device is lower than a threshold voltage of the first pass-gate device and the second pass-gate device.

2. The SRAM cell according to claim 1 , wherein the first pass-gate device and the second pass-gate device respectively comprise a first channel region, the first pull-down device and the second pull-down device respectively comprise a second channel region, and a dosage of the first channel region and a dosage of the second channel region are the same.

3. The SRAM cell according to claim 1 , wherein the first pull-up device, the second pull-up device, the first pull-down device, the second pull-down device, the first pass-gate device, and the second pass-gate device construct a 6T-SRAM.

4. The SRAM cell according to claim 3 , wherein a width of an active region of the first pull-up device, the second pull-up device, the first pull-down device, the second pull-down device, the first pass-gate device, and the second pass-gate device are the same.

5. The SRAM cell according to claim 1 , further comprising a third pass-gate device and a fourth pass-gate device.

6. The SRAM cell according to claim 5 , wherein the first pull-up device and the second pull-up device respectively comprise a first active region, the first pull-down device, the second pull-down device, the first pass-gate device, and the second pass-gate device respectively comprise a second active region, the third pass-gate device and the fourth pass-gate device respectively comprise a third active region, and widths of the first active regions, the second active regions, and the third active regions are different from each other.

7. The SRAM cell according to claim 5 , wherein the first pull-up device and the second pull-up device, the first pull-down device, the second pull-down device, the first pass-gate device, and the second pass-gate device are formed in between the third pass-gate device and the fourth pass-gate device to construct an 8T-dual port SRAM.

8. The SRAM cell according to claim 1 , further comprising a first read pass-gate device and a first read pull-down device.

9. The SRAM cell according to claim 8 , wherein the first pull-up device and the second pull-up device respectively comprise a first active region, the first pull-down device, the second pull-down device, the first pass-gate device, and the second pass-gate device respectively comprise a second active region, the first read pass-gate device and the first read pull-down device respectively comprise a third active region, and widths of the first active regions, the second active regions, and the third active regions are different from each other.

10. The SRAM cell according to claim 8 , wherein the first pull-up device, the second pull-up device, the first pull-down device, the second pull-down device, the first pass-gate device and the second pass-gate device are formed on a same side of the first read pass-gate device and the first read pull-down device to construct an 8T register file SRAM.

11. The SRAM cell according to claim 8 , further comprising a second read pass-gate device and a second read pull-down device, and the first pull-up device, the second pull-up device, the first pull-down device, the second pull-down device, the first pass-gate device, the second pass-gate device, the first read pass-gate device, the second read pass-gate device, the first read pull-down device, and the second read pull-down device construct a 10T register file SRAM.

12. The SRAM cell according to claim 11 , wherein the first pull-up device and the second pull-up device respectively comprise a first active region, the first pull-down device, the second pull-down device, the first pass-gate device, and the second pass-gate device respectively comprise a second active region, the first read pass-gate device, the second read pass-gate device, the first read pull-down device, and the second read pull-down device respectively comprise a third active region, and widths of the first active regions, the second active regions, and the third active regions are different from each other.

13. A method for manufacturing a SRAM cell, comprising:
providing a substrate comprising a plurality of active regions formed thereon, the active regions being extended along a first direction and arranged along a second direction;
forming a plurality of gate layers crossing the active regions to define a first pull-up device, a second pull-up device, a first pull-down device comprising a first conductivity type, a second pull-down device comprising the first conductivity type, a first pass-gate device comprising the first conductivity type and a second pass-gate device comprising the first conductivity type;
performing a first LDD doping to the first pass-gate device and the second pass gate device to form first LDDs at two sides of the gate layer of the first pass-gate device and at two sides of the gate layer of the second pass-gate device, and the first LDD doping comprising the first conductivity type; and
performing a second LDD doping after the first LDD doping to the first pull-down device and the second pull-down device to form second LDDs at two sides of the gate layer of the first pull-down device and at two sides of the gate layer of the second pull-down device, the second LDD doping comprising the first conductivity type, and a dosage of the second LDD doping being equal to or larger than a dosage of the first LDD doping.

14. The method for manufacturing the SRAM cell according to claim 13 , wherein the dosage of the first LDD doping is 1E14-1E15 cm −2 .

15. The method for manufacturing the SRAM cell according to claim 14 , wherein the first LDD doping is also performed to the first pull-down device and the second pull-down device.

16. The method for manufacturing the SRAM cell according to claim 14 , wherein the second LDD doping comprises arsenic (As), and a dosage of the second LDD doping is 1E14-1E15 cm −2 .

17. The method for manufacturing the SRAM cell according to claim 14 , wherein the first pull-down device and the second pull-down device are protected from the first LDD doping, and the second LDD doping comprises As, a dosage of the second LDD doping is 2E14-2E15 cm −2 .

18. The method for manufacturing the SRAM cell according to claim 13 , wherein the second LDD doping comprises solid phase diffusion.

19. The method for manufacturing the SRAM cell according to claim 13 , wherein the active regions comprise first active regions comprising the first conductivity type and second active regions comprising a second conductivity type, th

Assignees

• United Microelectronics Corp

Inventors

• Lu Tien-Yu
• Chen Chang-Hung
• Huang Chun-Hsien
• Wang Han-Tsun
• Yan Jheng-Tai
• Kuo Yu-Tse

Classifications

• H01L27/105

  Electricity · mapped topic

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• G11C11/418

  Address circuits · CPC title