Pseudo dual port memory using a dual port cell and a single port cell with associated valid data bits and related methods

Patent metadata

Field	Value
Publication number	US-9311990-B1
Application number	US-201414573106-A
Country	US
Kind code	B1
Filing date	Dec 17, 2014
Priority date	Dec 17, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A pseudo dual port memory includes a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality of addressed locations, and a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed locations. A valid data storage unit is configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells. Control circuitry is configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells. The control circuitry performs a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updates corresponding valid bits in the valid data storage unit, and performs a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

First claim

That which is claimed is:

1. A pseudo dual port memory comprising:
a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality of addressed locations;
a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed locations;
a valid data storage unit configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells; and
control circuitry configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells by
performing a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updating corresponding valid bits in the valid data storage unit, and
performing a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

2. The pseudo dual port memory according to claim 1 wherein the simultaneous write operation is performed in a single clock cycle.

3. The pseudo dual port memory according to claim 1 wherein the parallel read operation is performed in a single clock cycle.

4. The pseudo dual port memory according to claim 1 wherein the set of dual port memory cells comprises a matrix of 8T memory cells coupled together.

5. The pseudo dual port memory according to claim 1 wherein the set of single port memory cells comprises a matrix of 6T memory cells coupled together.

6. The pseudo dual port memory according to claim 1 wherein the valid data storage unit comprises a plurality of flip flop circuits.

7. The pseudo dual port memory according to claim 1 wherein the number of valid bits of the valid data storage unit corresponds to the number of stored data words of the set of dual port memory cells and the set of single port memory cells.

8. A dual port static random access memory (SRAM) comprising:
a pseudo dual port memory core comprising a matrix of memory cells coupled in rows and columns including
a set of dual port memory cells configured to store data words in each of a plurality of addressed locations, and
a set of single port memory cells configured to store data words in each of a plurality of addressed locations;

a valid data storage unit configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells; and
control circuitry, in connection with the row decoder and column decoder, configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells by
performing a simultaneous write operation at respective addressed locations of the set of dual port memory cells and the set of single port memory cells, and updating corresponding valid bits in the valid data storage unit, and
performing a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

9. The dual port SRAM architecture according to claim 8 wherein the set of dual port memory cells have a read port and a write port, and the set of single port memory cells have a read/write port; and wherein the control circuitry is configured to perform the simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and perform the parallel read operation using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells.

10. The dual port SRAM architecture according to claim 8 wherein the simultaneous write operation is performed in a single clock cycle.

11. The dual port SRAM architecture according to claim 8 wherein the parallel read operation is performed in a single clock cycle.

12. The dual port SRAM architecture according to claim 8 wherein the set of dual port memory cells comprises a matrix of 8T memory cells coupled together.

13. The dual port SRAM architecture according to claim 8 wherein the set of single port memory cells comprises a matrix of 6T memory cells coupled together.

14. The dual port SRAM architecture according to claim 8 wherein the valid data storage unit comprises a plurality of flip flop circuits.

15. The dual port SRAM architecture according to claim 8 wherein the number of valid bits of the valid data storage unit corresponds to the number of stored data words of the set of dual port memory cells and the set of single port memory cells.

16. A method of implementing a pseudo dual port memory, the method comprising:
addressing locations in a set of dual port memory cells having a read port and a write port, and in a set of single port memory cells having a read/write port, to store data words therein;
storing valid bits, corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells in a valid data storage unit; and
accessing, with control circuitry, the addressed locations of the set of dual port memory cells and the set of single port memory cells by
performing a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updating corresponding valid bits in the valid data storage unit, and
performing a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

17. The method according to claim 16 wherein the simultaneous write operation is performed in a single clock cycle.

18. The method according to claim 16 wherein the parallel read operation is performed in a single clock cycle.

19. The method according to claim 16 wherein the set of dual port memory cells comprises a matrix of 8T memory cells coupled together.

20. The method according to claim 16 wherein the set of single port memory cells comprises a matrix of 6T memory cells coupled together.

21. The method according to claim 16 wherein the valid data storage unit comprises a plurality of flip flop circuits.

22. The method according to claim 16 wherein the number of valid bits of the valid data storage unit corresponds to the number of stored data words of the set of dual port memory cells and the set of single port memory cells.

Assignees

• St Microelectronics Int Nv

Inventors

• Rawat Harsh
• Jain Piyush

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C7/1075

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title