Sigma delta modulator, integrated circuit and method therefor

Patent metadata

Field	Value
Publication number	US-11271585-B2
Application number	US-202017065731-A
Country	US
Kind code	B2
Filing date	Oct 8, 2020
Priority date	Oct 28, 2019
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC comprises or is operably coupled to, a calibration circuit (650, 840) coupled to an input and an output of the at least one pair of comparator latches (336, 356) and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches (336, 356) in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.

First claim

The invention claimed is:

1. A N-bit continuous-time sigma-delta modulator, SDM, comprising:
an input configured to receive an input analog signal;
a first summing junction configured to subtract a feedback analog signal from the input analog signal;
a loop filter configured to filter an output signal from the first summing junction:
an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal to a digital output signal where each 1-bit ADC comprises at least one pair of comparator latches; and
a feedback path for routing the digital output signal to the first summing junction, wherein the feedback path comprises a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form;
wherein the ADC comprises, or is operably coupled to, a calibration circuit coupled to an input and an output of the at least one pair of comparator latches and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches in a time-interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.

2. The N-bit continuous-time SDM of claim 1 wherein the calibration circuit is configured to operate using at least two-stages, where a first stage performs a coarse calibration of the at least a pair of comparator latches and at least one second stage performs a fine calibration of the at least a pair of comparator latches.

3. The N-bit continuous-time SDM of claim 1 wherein the calibration circuit comprises or is operably coupled to a coarse calibration circuit and the N-bit continuous-time SDM further comprises a master controller configured to apply one or more control signals to select one or more respective comparator latch of the at least a pair of comparator latches for calibrating.

4. The N-bit continuous-time SDM of claim 3 wherein the master controller selects either a coarse calibration or fine calibration mode and selects a respective comparator latch of the at least a pair of comparator latches and sweeps a calibration code of successively modified steps that is input to the selected the respective comparator latch to identify one of a coarse calibration code, a fine calibration code.

5. The N-bit continuous-time SDM of claim 4 wherein the calibration code is swept from a minus full scale to a positive full scale with a minimum step that is input to the selected the respective comparator latch to identify one of a coarse calibration code, a fine calibration code, and in response to a correct calibration code being detected, the calibration circuit selects a code value that is equal to a correct calibration code or at least one less than the correct calibration code for use in a normal mode of operation.

6. The N-bit continuous-time SDM of claim 1 wherein the calibrated comparator error of the comparator latches comprises at least one from a group of: a calibrated comparator offset error, a calibrated comparator timing error, a calibrated comparator reference error.

7. The N-bit continuous-time SDM of claim 1 wherein the calibration circuit is configured to operate in a one-stage manner that is sufficient to capture a comparator error of the comparator latches, whereby the one-stage is either:
only a coarse calibration circuit configured to perform a coarse calibration of the at least a pair of comparator latches;
only a fine calibration circuit with a calibration DAC configured to perform a fine calibration of the at least a pair of comparator latches.

8. The N-bit continuous-time SDM of claim 1 wherein the calibration of the comparator error comprises the calibration circuit being configured to apply:
control signals to the comparator latches to operate the pair of comparator latches in a time-interleaved manner; and
apply iteratively a first coarse calibration signal to a first latch followed by a second coarse calibration signal to a second latch of the pair of comparator latches, until the coarse calibration is complete;
apply iteratively a first fine calibration signal to the first latch followed by a second fine calibration signal to the second latch of the pair of comparator latches and repeat until the fine calibration is complete,
wherein only the output of the latch under calibration is sampled and provided to the calibration circuit.

9. The N-bit continuous-time SDM of claim 1 wherein the calibration of the comparator error comprises a calibration of at least one of the following: a comparator offset, a comparator timing error, a comparator reference error.

10. The N-bit continuous-time SDM of claim 1 wherein the feedback path and the loop filter of the N-bit continuous-time SDM are disconnected from the quantizer to perform a calibration mode of operation and the comparator error calibration performed on the quantizer.

11. The N-bit continuous-time SDM of claim 2 wherein the fine calibration circuit is combined for two time-interleaved comparator latches of the at least a pair of comparator latches.

12. The N-bit continuous-time SDM of claim 11 wherein the fine calibration circuit is implemented as a current steering calibration digital-to-analog converter, DAC.

13. The N-bit continuous-time SDM of claim 12 further comprising a multiplexer wherein an input to the current steering DAC is configured to toggle between two fine codes by the multiplexer.

14. An integrated circuit comprising a N-bit continuous-time sigma-delta modulator, SDM, comprising:
an input configured to receive an input analog signal;
a first summing junction configured to subtract a feedback analog signal from the input analog signal;
a loop filter configured to filter an output signal from the first summing junction:
an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal and every 1-bit ADC comprising at least one pair of comparator latches; and
a feedback path for routing the digital output signal to the first summing junction, wherein the feedback path comprises a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form;
wherein the ADC comprises, or is operably coupled to, a calibration circuit coupled to an input and an output of the at least one pair of comparator latches and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches in a time-interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.

15. A method for calibrating a N-bit continuous-time sigma-delta modulator, SDM, the method comprising:
receiving an input analog signal;
subtracting a feedback analog signal from the input analog signal in a first summing junction;
filtering an output signal from the first summing junction:
converting the filtered analog output signal to a digital output signal in an N-bit analog-to-digital converter, ADC;
feeding back the digital output signal to the first summing junction, via a digital-to-analog converter, DAC, converting the digital output signal to an analog form;
applying respective calibration signals to individual comparator latches of at least one pair of comparator latches in a time-interleaved manner, and
calibrating a comparator error of the comparator latches in response to a latched output of the respective calibration signals in response to a latched ou

Assignees

• Nxp Bv

Inventors

• Zhang Chenming
• Breems Lucien Johannes
• Bolatkale Muhammed

Classifications

• H03M3/02 Primary

  Delta modulation, i.e. one-bit differential modulation {(H03M3/30 takes precedence)} · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M3/38

  Calibration · CPC title

• H03M3/47 Primary

  using time-division multiplexing · CPC title

• H03M3/424 Primary

  the quantiser being a multiple bit one · CPC title