Current digital-to-analog converter with high-impedance output

Patent metadata

Field	Value
Publication number	US-11271583-B2
Application number	US-202016945288-A
Country	US
Kind code	B2
Filing date	Jul 31, 2020
Priority date	Dec 6, 2019
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A differential output current digital-to-analog converter (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

First claim

What is claimed is:

1. A differential output current digital-to-analog converter (IDAC) circuit comprising:
a delta-sigma modulator configured to receive a digital input signal;
a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation;
a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC; and
an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

2. The IDAC of claim 1 , wherein the plurality of DAC elements comprise:
a first plurality of DAC elements coupled between a supply voltage and the pair of output terminals; and
a second plurality of DAC elements coupled between a ground voltage and the pair of output terminals.

3. The IDAC of claim 1 , wherein each of the plurality of DAC elements are coupled between one of the pair of output terminals and one of a first supply voltage and a second supply voltage.

4. The IDAC of claim 1 , wherein:
the output impedance comprises a switched-tapped output impedance having a plurality of impedance elements and a plurality of taps comprising a respective tap at each end of each of the plurality of impedance elements;
the IDAC further comprises a plurality of selectable switches, each of the plurality of selectable switches coupled between a respective tap of the plurality of taps and one of a supply voltage and a ground voltage; and
the control circuitry is further configured to control the plurality of selectable switches responsive to the delta-sigma modulator.

5. The IDAC of claim 4 , wherein the individual impedances of the plurality of impedance elements are uniform.

6. The IDAC of claim 4 , wherein the individual impedances of the plurality of impedance elements are non-uniform.

7. A circuit comprising:
a delta-sigma modulator configured to receive a digital input signal;
circuitry configured to generate a differential output signal at an output comprising a first output terminal and a second output terminal, the circuitry comprising:
a switched-tapped output impedance having a plurality of impedance elements and a plurality of taps comprising a respective tap at each end of each of the plurality of impedance elements, wherein each tap is coupled to a first power supply voltage via a respective tap switch; and
wherein:
each of the first output terminal and the second output terminal is coupled to a second power supply voltage via a respective current source; and
the tap switches are responsive to the delta-sigma modulator.

8. The circuit of claim 7 , wherein the individual impedances of the plurality of impedance elements are uniform.

9. The circuit of claim 7 , wherein the individual impedances of the plurality of impedance elements are non-uniform.

10. A method comprising:
receiving a digital input signal at a delta-sigma modulator;
performing a digital-to-analog converter (DAC) decode operation responsive to the delta-sigma modulator; and
generating, by a plurality of DAC elements and responsive to the DAC decode operation, a differential output current signal based on the digital input signal to:
a load coupled to a pair of output terminals of a differential output current digital-to-analog converter (IDAC) circuit; and
an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

11. The method of claim 10 , wherein the plurality of DAC elements comprise:
a first plurality of DAC elements coupled between a supply voltage and the pair of output terminals; and
a second plurality of DAC elements coupled between a ground voltage and the pair of output terminals.

12. The method of claim 10 , wherein each of the plurality of DAC elements are coupled between one of the pair of output terminals and one of a first supply voltage and a second supply voltage.

13. The method of claim 10 , wherein:
the output impedance comprises a switched-tapped output impedance having a plurality of impedance elements and a plurality of taps comprising a respective tap at each end of each of the plurality of impedance elements;
the IDAC further comprises a plurality of selectable switches, each of the plurality of selectable switches coupled between a respective tap of the plurality of taps and one of a supply voltage and a ground voltage; and
the method further comprising controlling the plurality of selectable switches responsive to the delta-sigma modulator.

14. The method of claim 13 , wherein the individual impedances of the plurality of impedance elements are uniform.

15. The method of claim 13 , wherein the individual impedances of the plurality of impedance elements are non-uniform.

16. A method comprising:
receiving a digital input signal at a delta-sigma modulator;
generating a differential output signal at an output comprising a first output terminal and a second output terminal using circuitry comprising:
a switched-tapped output impedance having a plurality of impedance elements and a plurality of taps comprising a respective tap at each end of each of the plurality of impedance elements, wherein each tap is coupled to a first power supply voltage via a respective tap switch; and
wherein:
each of the first output terminal and the second output terminal is coupled to a second power supply voltage via a respective current source; and
the tap switches are responsive to the delta-sigma modulator.

17. The method of claim 16 , wherein the individual impedances of the plurality of impedance elements are uniform.

18. The method of claim 16 , wherein the individual impedances of the plurality of impedance elements are non-uniform.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Melanson John L
• Gaboriau Johann G
• Zhu Lei
• Shum Wai-Shun
• Fei Xiaofan
• Yin Leyi

Classifications

• H03M3/502

  Details of the final digital/analogue conversion following the digital delta-sigma modulation · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H03M1/742 Primary

  using current sources as quantisation value generators · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• H04R2499/11

  Transducers incorporated or for use in hand-held devices, e.g. mobile phones, PDA's, camera's · CPC title