Current digital-to-analog converter with warming of digital-to-analog converter elements

Patent metadata

Field	Value
Publication number	US-11043959-B1
Application number	US-202016942062-A
Country	US
Kind code	B1
Filing date	Jul 29, 2020
Priority date	Dec 6, 2019
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

First claim

What is claimed is:

1. A differential output current digital-to-analog (IDAC) circuit comprising:
a delta-sigma modulator configured to receive a digital input signal;
a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation;
a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC; and
a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

2. The IDAC of claim 1 , wherein the control circuit is further configured to control the plurality of DAC elements and the plurality of warming switches in order to maintain one or more DAC elements in a biased, output-disabled state.

3. The IDAC of claim 2 , wherein the control circuit is further configured to, responsive to an increase in a magnitude of the digital input signal:
transition one or more DAC elements from the biased, output-disabled state to the output-enabled state; and
transition one or more DAC elements from a de-biased, output-disabled state to the biased, output-disabled state.

4. The IDAC of claim 3 , wherein the control circuit is further configured to maintain constant the number of DAC elements in the biased, output-disabled state in response to the decrease in the magnitude of the digital input signal.

5. The IDAC of claim 2 , wherein the control circuit is further configured to, responsive to a decrease in a magnitude of the digital input signal:
transition one or more DAC elements from the biased, output-disabled state to the de-biased, output-disabled state; and
transition one or more DAC elements from the output-enabled state to the biased, output-disabled state.

6. The IDAC of claim 3 , wherein the control circuit is further configured to maintain constant the number of DAC elements in the biased, output-disabled state in response to the decrease in the magnitude of the digital input signal.

7. The IDAC of claim 2 , wherein the control circuit is further configured to maintain a number of DAC elements in the biased, output-disabled state based on a settling time of the plurality of DAC elements.

8. The IDAC of claim 2 , wherein the control circuit is further configured to maintain a number of DAC elements in the biased, output-disabled state based on an expected or allowable sample-to-sample change in a quantized signal generated by the delta-sigma modulator.

9. The IDAC of claim 2 , wherein the control circuit is further configured to maintain a number of DAC elements in the biased, output-disabled state based on a slew rate of the digital input signal.

10. The IDAC of claim 2 , wherein the control circuit is further configured to maintain a number of DAC elements in the biased, output-disabled state based on a frequency of the digital input signal.

11. The IDAC of claim 2 , wherein the control circuit is further configured to maintain a number of DAC elements in the biased, output-disabled state based on a magnitude of the digital input signal.

12. The IDAC of claim 2 , wherein the control circuit is further configured to maintain a number of DAC elements in the biased, output-disabled state based on noise present in the digital input signal.

13. The IDAC of claim 2 , wherein the delta-sigma modulator is further configured to constrain values of output samples of a quantized signal generated by the delta-sigma modulator based on a number of DAC elements maintained in the biased, output-disabled state.

14. A method in a differential output current digital-to-analog (IDAC) circuit comprising a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, the method comprising:
selectively controlling each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

15. The method of claim 14 , further comprising controlling the plurality of DAC elements and the plurality of warming switches in order to maintain one or more DAC elements in a biased, output-disabled state.

16. The method of claim 15 , further comprising, responsive to an increase in a magnitude of the digital input signal:
transitioning one or more DAC elements from the biased, output-disabled state to the output-enabled state; and
transitioning one or more DAC elements from a de-biased, output-disabled state to the biased, output-disabled state.

17. The method of claim 16 , further comprising maintaining constant the number of DAC elements in the biased, output-disabled state in response to the decrease in the magnitude of the digital input signal.

18. The method of claim 15 , further comprising, responsive to a decrease in a magnitude of the digital input signal:
transitioning one or more DAC elements from the biased, output-disabled state to the de-biased, output-disabled state; and
transitioning one or more DAC elements from the output-enabled state to the biased, output-disabled state.

19. The method of claim 16 , further comprising maintaining constant the number of DAC elements in the biased, output-disabled state in response to the decrease in the magnitude of the digital input signal.

20. The method of claim 15 , further comprising maintaining a number of DAC elements in the biased, output-disabled state based on a settling time of the plurality of DAC elements.

21. The method of claim 15 , further comprising maintaining a number of DAC elements in the biased, output-disabled state based on an expected or allowable sample-to-sample change in a quantized signal generated by the delta-sigma modulator.

22. The method of claim 15 , further comprising maintaining a number of DAC elements in the biased, output-disabled state based on a slew rate of the digital input signal.

23. The method of claim 15 , further comprising maintaining a number of DAC elements in the biased, output-disabled state based on a frequency of the digital input signal.

24. The method of claim 15 , further comprising maintaining a number of DAC elements in the biased, output-disabled state based on a magnitude of the digital input signal.

25. The method of claim 15 , further comprising maintaining a number of DAC elements in the biased, output-disabled state based on noise present in the digital input signal.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Melanson John L
• Gaboriau Johann G
• Zhu Lei
• Shum Wai-Shun
• Fei Xiaofan
• Yin Leyi

Classifications

• H03M3/502

  Details of the final digital/analogue conversion following the digital delta-sigma modulation · CPC title

• H03M3/376

  Prevention or reduction of switching transients, e.g. glitches · CPC title

• H03M3/374

  Relaxation of settling time constraints, e.g. slew rate enhancement · CPC title

• H03M1/742 Primary

  using current sources as quantisation value generators · CPC title

• H04R3/00 Primary

  Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) · CPC title