Digital to analog converter circuit and digital to analog conversion method

Patent metadata

Field	Value
Publication number	US-9853658-B1
Application number	US-201715639825-A
Country	US
Kind code	B1
Filing date	Jun 30, 2017
Priority date	May 17, 2017
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A DAC circuit includes: a PWM encoding circuit for converting a digital signal to first and second PWM signals, whereby a combination of the first and second PWM signals becomes a PWM encoded signal of at least 3 levels including a positive, a zero and a negative level, wherein the digital signal represents a number in a numerical range; and a demodulation circuit for generating the analog signal according to the first and second PWM signals. The first and second PWM signals have a minimum duty larger than 0 when the digital signal represents a middle number in the numerical range. The zero level of the combination of the first and second PWM signals has a duty which decreases as a difference between the number represented by the digital signal and the middle number increases.

First claim

What is claimed is:

1. A Digital to Analog Converter (DAC) circuit, configured to operably convert a digital signal to an analog output signal, wherein the digital signal is an input signal to the DAC circuit or a modulated signal generated from the input signal, the digital signal representing a number in a numerical range, the DAC circuit comprising:
a Pulse Width Modulation (PWM) encoding circuit, configured to operably convert the digital signal to a first PWM signal and a second PWM signal, whereby a combination of the first PWM signal and the second PWM signal becomes a PWM encoded signal of at least 3 levels including a positive, a zero and a negative level, wherein in one PWM cycle period, the first PWM signal includes a first predetermined number of rising edges and falling edges, and the second PWM signal includes a second predetermined number of rising edges and falling edges, wherein when the digital signal represents a middle number in the numerical range, the first PWM signal has a minimum duty larger than 0 and the second PWM signal has a minimum duty larger than 0; and
a demodulation circuit, configured to operably generate the analog output signal according to the first and the second PWM signals,
wherein the zero level of the PWM encoded signal has a duty which decreases as an absolute difference between the number represented by the digital signal and the middle number increases.

2. The DAC circuit of claim 1 , wherein the demodulation circuit includes:
a current signal converter circuit, configured to operably generate a current output signal of at least 3 levels according to the first and the second PWM signals, wherein when the PWM encoded signal is at the zero level, the current output signal is a zero level current, wherein a noise of the zero level current is smaller than ⅕ of a noise of a current of any other level; and
a filter circuit, configured to operably filter the current output signal to generate the analog output signal.

3. The DAC circuit of claim 2 , wherein the noise of the zero level current is smaller than 1/10 of the noise of the current of any other level.

4. The DAC circuit of claim 2 , wherein the zero level current is smaller than 1/10 of the current of any other level.

5. The DAC circuit of claim 1 , wherein in one PWM cycle period, for each number represented by the digital signal, each of the first and the second PWM signals includes one and only one rising edge and one and only one falling edge.

6. The DAC circuit of claim 1 , wherein when the number represented by the digital signal is larger than the middle number, a duty of the first PWM signal increases as the absolute difference between the number represented by the digital signal and the middle number increases, and when the number represented by the digital signal is smaller than the middle number, a duty of the second PWM signal increases as the absolute difference between the number represented by the digital signal and the middle number increases.

7. The DAC circuit of claim 2 , wherein the current signal converter circuit includes:
a current source circuit, configured to operably generate a unit current, and
plural conversion switches coupled to the current source circuit, wherein the first and the second PWM signals operate the plural conversion switches to switch a current path of the unit current for generating the current output signal with at least 3 levels, wherein when the PWM encoded signal is at the zero level, the current output signal is disconnected from the current source circuit such that the current output signal is the zero level current.

8. The DAC circuit of claim 1 , wherein each of the first and the second PWM signals has a blank time slot in the PWM cycle period, and for each number represented by the digital signal, the first PWM signal includes a first predetermined number of rising edges and falling edges outside of the blank time slot in the PWM cycle period, and the second PWM signal includes a second predetermined number of rising edges and falling edges outside of the blank time slot in the PWM cycle period.

9. The DAC circuit of claim 1 , further including:
an interpolation filter circuit, configured to operably filter and up-sample the input signal to generate an interpolation filtered signal; and
a Sigma-Delta Modulation (SDM) circuit, configured to operably modulate the interpolation filtered signal with a multi-bit sigma-delta modulation for generating the modulated signal, wherein the modulated signal includes multiple bits.

10. The DAC circuit of claim 1 , wherein a duty of the first PWM signal determines a duty of the positive level of the PWM encoded signal, and a duty of the second PWM signal determines a duty of the negative level of the PWM encoded signal.

11. A digital to analog conversion method, for converting a digital signal to an analog output signal, wherein the digital signal is an input signal to a DAC circuit or a modulated signal generated from the input signal, the digital signal representing a number in a numerical range, the method comprising:
converting the digital signal to a first PWM signal and a second PWM signal, whereby a combination of the first PWM signal and the second PWM signal becomes a PWM encoded signal of at least 3 levels including a positive, a zero and a negative level, wherein in one PWM cycle period, the first PWM signal includes a first predetermined number of rising edges and falling edges, and the second PWM signal includes a second predetermined number of rising edges and falling edges, wherein when the digital signal represents a middle number in the numerical range, the first PWM signal has a minimum duty larger than 0 and the second PWM signal has a minimum duty larger than 0; and
generating the analog output signal according to the first and the second PWM signals,
wherein the zero level of the PWM encoded signal has a duty which decreases as an absolute difference between the number represented by the digital signal and the middle number increases.

12. The digital to analog conversion method of claim 11 , wherein the step of generating the analog output signal includes:
generating a current output signal of at least 3 levels according to the first and the second PWM signals, wherein when the PWM encoded signal is at the zero level, the current output signal is a zero level current, wherein a noise of the zero level current is smaller than ⅕ of a noise of a current of any other level; and
filtering the current output signal to generate the analog output signal.

13. The digital to analog conversion method of claim 12 , wherein the noise of the zero level current is smaller than 1/10 of the noise of the current of any other level.

14. The digital to analog conversion method of claim 12 , wherein the zero level current is smaller than 1/10 of the current of any other level.

15. The digital to analog conversion method of claim 11 , wherein in one PWM cycle period, for each number represented by the digital signal, each of the first and the second PWM signals includes one and only one rising edge and one and only one falling edge.

16. The digital to analog conversion method of claim 11 , wherein the step of converting the digital signal to a first PWM signal and a second PWM signal further includes:
when the number represented by the digital signal is larger than the middle number, increasing a duty of the first PWM signal as the absolute difference between the digital signal and the middle number increases; and
when the number represented by the digital signal is smaller than the middle number, increasin

Assignees

• Richtek Technology Corp

Inventors

• Hsiao Ming-Jun
• Chen zong-yi

Classifications

• H03M3/50 Primary

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title

• H03M3/438

  the modulator having a higher order loop filter in the feedforward path · CPC title

• H03M1/504 Primary

  using pulse width modulation · CPC title

• H03M3/506

  the final digital/analogue converter being constituted by a pulse width modulator · CPC title