High performance interconnect

Patent metadata

Field	Value
Publication number	US-11269793-B2
Application number	US-202016937499-A
Country	US
Kind code	B2
Filing date	Jul 23, 2020
Priority date	Oct 22, 2012
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

First claim

What is claimed is:

1. An apparatus comprising:
a first system component comprising:
a memory comprising non-volatile memory;
an interface to couple to a second system component via a link, wherein the link comprises a set of physical lanes, and the link supports a cache-coherent protocol;
a protocol engine for the cache-coherent protocol, the protocol engine to:
receive a set of write requests to update data at addresses of the non-volatile memory;
receive a message, wherein the message comprises:
an opcode to identify the message as a persistent memory flush request for flushing the non-volatile memory,
a destination identifier to identify a destination of the message, and
a requester identifier to identify a source of the message; and

a memory controller to support coherent management of data in the memory in association with the cache-coherent protocol, wherein the memory controller is to:
update the non-volatile memory, responsive to the persistent memory flush request, to complete all outstanding writes in the set of write requests.

2. The apparatus of claim 1 , wherein the protocol engine is further to send a response to the second system component to indicate completion of the persistent memory flush request.

3. The apparatus of claim 2 , wherein the protocol engine is to send the response to guarantee that the update is performed or in process of being performed.

4. The apparatus of claim 1 , wherein completion of the outstanding writes causes data of the non-volatile memory to be modified based on the set of write requests.

5. The apparatus of claim 1 , further comprising a coherency agent to determine coherency state of data in the memory.

6. The apparatus of claim 1 , wherein the persistent memory flush request is based on a power-down event.

7. An apparatus comprising:
a first system component comprising:
an interface to couple to a second system component via a link, wherein the link comprises a plurality of physical lanes, and the link supports a cache-coherent protocol;
protocol circuitry to:
send a message to the second system component over the link, wherein the message comprises:
an opcode to identify the message as a persistent memory flush request,
a destination identifier to identify the second system component, and
a source identifier to identify the first system component, wherein the persistent memory flush request requests the second system component to complete all outstanding writes to persistent memory of the second system component based on the persistent memory flush request; and

receive a response to the message from the second system component over the link, wherein the response indicates completion of the persistent memory flush request.

8. The apparatus of claim 7 , wherein the first system component is to send at least one write in a set of write requests to the second system component over the link to update data at addresses of the non-volatile memory, and the outstanding writes comprise at least one request from the set of write requests.

9. The apparatus of claim 7 , wherein the outstanding writes comprise a plurality of outstanding writes.

10. The apparatus of claim 9 , wherein the outstanding writes comprise writes to a plurality of different addresses in the non-volatile memory.

11. The apparatus of claim 7 , wherein the persistent memory flush request is broadcast to a plurality of system components including the second system component.

12. The apparatus of claim 7 , further comprising a home agent.

13. A method comprising:
receiving a set of write requests to update data at addresses of a non-volatile memory of a first component, wherein the set of write requests are received over a link, the first component is coupled to a second component by the link, the link comprises a plurality of physical lanes, and the link supports a cache-coherent protocol;
receiving a message comprising:
an opcode to identify the message as a persistent memory flush request for flushing the non-volatile memory,
a destination identifier to identify a destination of the message, and
a requester identifier to identify a source of the message; and

updating the non-volatile memory to complete all outstanding writes in the set of write requests based on the persistent memory flush request.

14. The method of claim 13 , further comprising sending a response to the second system component to indicate completion of the persistent memory flush request.

15. A method comprising:
sending a message from a first component to a second component over a link, wherein the link couples the first component and second component, the link comprises a set of physical lanes, and the link carried data according to a cache-coherent protocol, and wherein the message comprises:
an opcode to identify the message as a persistent memory flush request,
a destination identifier to identify the second component, and
a source identifier to identify the first component, wherein the persistent memory flush request requests the second component to complete all outstanding writes to persistent memory of the second component based on the persistent memory flush request; and

receiving a response to the message from the second component over the link, wherein the response indicates completion of the persistent memory flush request.

16. The method of claim 15 , further comprising sending a write request to the second component over the link, wherein the outstanding writes comprise the write request.

17. A system comprising:
a first device; and
a second device coupled to the first device by a link, wherein the link comprises a set of physical lanes, and the link supports a cache-coherent protocol, wherein the second device comprises:
a memory comprising non-volatile memory;
a protocol engine for the cache-coherent protocol, the protocol engine to:
receive a set of write requests to update data at addresses of the non-volatile memory;
receive a message from the first device over the link, wherein the message comprises:
an opcode to identify the message as a persistent memory flush request for flushing the non-volatile memory,
a destination identifier to identify a destination of the message, and
a requester identifier to identify a source of the message; and

a memory controller to support coherent management of data in the memory, wherein the memory controller is to:
update the non-volatile memory, responsive to the persistent memory flush request, to complete all outstanding writes in the set of write requests.

18. The system of claim 17 , wherein the second device comprises a processor.

19. The system of claim 17 , wherein the second device comprises an accelerator.

20. The system of claim 17 , wherein the second device comprises a graphics device.

21. The system of claim 17 , wherein the first device comprises a system on chip (SoC).

Assignees

• Intel Corp

Inventors

• Safranek Robert J
• Blankenship Robert G
• Iyer Venkatraman
• Willey Jeff
• Beers Robert
• Jue Darren S
• Kumar Arvind A
• Das Sharma Debendra
• Swanson Jeffrey C
• Fahim Bahaa
• Geetha Vedaraman
• Spink Aaron T
• Spagna Fulvio
• Shah Rahul R
• Iyer Sitaraman V
• Nale William Harry
• Das Abhishek
• Johnson Simon P
• Dhillon Yuvraj S
• Liu Yen-Cheng
• Ramanujan Raj K
• Maddox Robert A
• Hum Herbert H
• Gupta Ashish

Classifications

• H04L12/56

  Packet switching systems · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F8/71

  Version control (security arrangements therefor G06F21/57); Configuration management · CPC title

• Y02D30/00

  Reducing energy consumption in communication networks · CPC title