Reference precharge system

Patent metadata

Field	Value
Publication number	US-11264959-B2
Application number	US-202016903030-A
Country	US
Kind code	B2
Filing date	Jun 16, 2020
Priority date	Jun 16, 2020
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

A precharge circuit comprises a gain amplifier, a comparator, a reservoir capacitor, a switch, a current source, and a switching network. The gain amplifier has a gain G 1 and receives an input voltage Vrefp. The gain amplifier outputs an amplified voltage G 1 Vrefp to the comparator, which compares G 1 Vrefp to a voltage across the reservoir capacitor. The comparator outputs a control signal for the switch based on the comparison. The switch couples the current source to the reservoir capacitor. The current from the current source charges the reservoir capacitor. The switching network couples the reservoir capacitor to an output of the precharge circuit during a first operating mode and provides the input voltage Vrefp to the output during a second operating mode.

First claim

What is claimed is:

1. An apparatus, comprising:
a gain amplifier coupled to a comparator and to a first voltage terminal;
a reservoir capacitor comprising a first terminal and, a second terminal wherein the comparator is further coupled to the first terminal;
a logic circuit coupled to the comparator and configured to generate a first control signal for a first switch and a second switch, wherein the first switch is configured to couple a current source to the first terminal of the reservoir capacitor, wherein the second switch is configured to couple a current sink to the second terminal of the reservoir capacitor;
a common mode feedback (CMFB) loop coupled to the second terminal of the reservoir capacitor, the first terminal of the reservoir capacitor, and a common mode voltage terminal, the CMFB loop configured to generate a second control signal for the current sink; and
a switching network configured to couple the first terminal of the reservoir capacitor to a first output and the second terminal of the reservoir capacitor to a second output based on a third control signal, and configured to couple the first voltage terminal to the first output and a second voltage terminal to the second output based on a fourth control signal.

2. The apparatus of claim 1 , wherein the switching network comprises:
a third switch configured to couple the first terminal of the reservoir capacitor to the first output;
a fourth switch configured to couple the second terminal of the reservoir capacitor to the second output;
a fifth switch configured to couple the first voltage terminal to the first output; and
a sixth switch configured to couple the second voltage terminal to the second output.

3. The apparatus of claim 2 , wherein the first and second outputs are coupled to an analog-to-digital converter (ADC), wherein the third control signal causes the third and fourth switches to be closed during a coarse charging portion of an integrating operation performed by the ADC, wherein the fourth control signal causes the fifth and sixth switches to be closed during a fine charging portion of the integrating operation performed by the ADC.

4. The apparatus of claim 1 , wherein the gain amplifier comprises:
an amplifier having a first input, a second input, and an amplifier output, wherein the first input is coupled to the first voltage terminal;
a first resistor coupled to the second voltage terminal and to the second input; and
a second resistor coupled to the second input and to the amplifier output.

5. The apparatus of claim 1 , wherein the first and second outputs are coupled to an analog-to-digital converter (ADC), wherein the first control signal causes the first and second switches to be closed during a sampling operation performed by the ADC.

6. The apparatus of claim 1 , wherein the CMFB loop generates the second control signal to adjust an amount of current through the current sink, such that a voltage on the common mode voltage terminal is substantially equal to half a voltage across the reservoir capacitor.

7. The apparatus of claim 1 , wherein the first and second outputs are coupled to a feedback capacitor in an analog-to-digital converter (ADC), wherein the current source is configured to charge the reservoir capacitor such that a voltage across the reservoir capacitor is approximately equal to:

G
⁡

(

Vrefp
-
Vrefn

)

=

(

1
+

C
⁢
d
⁢
a
⁢
c

C
⁢
r
⁢
e
⁢
s

)

⁢

(

Vrefp
-
Vrefn

)

where G represents an overall gain, Cdac represents a capacitance of the feedback capacitor, Cres represents a capacitance of the reservoir capacitor, Vrefp represents a voltage on the first voltage terminal, and Vrefn represents a voltage on the second voltage terminal.

8. The apparatus of claim 7 , wherein the gain amplifier has a gain G 1 , wherein the current source is configured to generate a charging current that is approximately equal to:

Vrefp
-
Vrefn

R

where R represents an internal resistance of the current source, wherein the overall gain G is substantially equal to:

G
⁢
1

+

t
⁢
d
⁢
e
⁢
l
⁢
a
⁢
y

R
⁢
C
⁢
r
⁢
e
⁢
s

where tdelay represents a delay between a time at which an output of the gain amplifier is substantially equal to the voltage across the reservoir capacitor and a time at which the first and second switches disconnect the current source and the current sink from the reservoir capacitor.

9. A precharge circuit, comprising:
a gain amplifier having a gain G 1 , the gain amplifier configured to receive an input voltage Vrefp and output an amplified voltage G 1 Vrefp;
a comparator configured to compare the amplified voltage G 1 Vrefp and a voltage across a reservoir capacitor, and further configured to generate a control signal based on the comparison;
a switch configured to couple a current source to the reservoir capacitor based on the control signal, wherein the current source is configured to generate a charging current for the reservoir capacitor; and
a switching network configured to couple the reservoir capacitor to an output during a coarse charging portion of an integration operation performed by an analog to digital converter (ADC), wherein the output is configured to be coupled to a capacitor in the ADC, wherein the switching network is further configured to provide the input voltage Vrefp to the capacitor during a fine charging portion of the integration operation.

10. The precharge circuit of claim 9 , wherein the input voltage Vrefp is a first input voltage, wherein the gain amplifier comprises:
an amplifier having a first input, a second input, and an amplifier output, wherein the first input is config

Assignees

• Texas Instruments Inc

Inventors

• Gupta Amit Kumar
• Cao Peng

Classifications

• H03F2203/45424

  the CMCL comprising a comparator circuit · CPC title

• H03F3/45659

  Controlling the loading circuit of the differential amplifier · CPC title

• H03F2200/78

  A comparator being used in a controlling circuit of an amplifier · CPC title

• H03F3/3035 Primary

  using differential amplifiers as phase-splitting elements · CPC title

• H03F2203/45418

  the CMCL comprising a resistor addition circuit · CPC title