Pipeline ADC and reference load balancing circuit and method to balance reference circuit load

Patent metadata

Field	Value
Publication number	US-9748965-B2
Application number	US-201514848499-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Sep 10, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects for a reference voltage signal, in which balancing capacitors are connected to a voltage source in a pipeline stage ADC sample time period to precharge the balancing capacitors using a voltage above the reference voltage, and a selected set of the precharged balancing capacitors is connected to provide charge to the output of the reference circuit during the second time period.

First claim

The following is claimed:

1. A balancing circuit to balance a load of a reference circuit with an output that provides a reference voltage signal to a load circuit in first and second time periods (S, H), the balancing circuit comprising:
capacitors;
a first circuit operative during the first time period to charge one or more of the capacitors using a voltage source; and
a second circuit operative during the first time period to select one or more of the charged capacitors according to an expected load of the load circuit in the second time period;
the first circuit operative during the second time period to connect the selected one or more capacitors to the output of the reference circuit.

2. The balancing circuit of claim 1 , wherein the voltage source has a voltage greater than the reference voltage signal.

3. The balancing circuit of claim 2 , wherein the first circuit includes:
first switches to connect the one or more capacitors to the voltage source during the first time period, and to disconnect the one or more capacitors from the voltage source during the second time period; and
second switches individually associated with a corresponding one of the capacitors, the individual second switches operative when a corresponding control signal is in a first state to selectively connect the corresponding capacitor to the output of the reference circuit, and the individual second switches operative when the corresponding control signal is in a second state to disconnect the corresponding capacitor from the output of the reference circuit;
wherein the second circuit is operative during the first time period to provide the control signals in the second state to the second switches, wherein the second circuit is operative during the second time period to selectively provide the control signals in the first state to a selected set of the second switches corresponding to the selected one or more capacitors, and wherein the second circuit is operative during the second time period to selectively provide the control signals in the second state to any remaining unselected second switches.

4. The balancing circuit of claim 3 , wherein the second circuit is operative during the first time period to select the one or more charged capacitors according to an amplitude of an input signal received by a converter stage of a pipeline analog to digital converter (ADC).

5. The balancing circuit of claim 4 , wherein the second circuit is operative during the first time period to select the one or more charged capacitors according to digital output signals from a stage ADC of the converter stage, wherein the digital output signals represent the amplitude of the input signal received by the converter stage during the first time period, and wherein the second circuit is operative during the second time period to generate the control signals according to the digital output signals from the stage ADC.

6. The balancing circuit of claim 2 , wherein the second circuit is operative during the first time period to select the one or more charged capacitors according to an amplitude of an input signal received by a converter stage of a pipeline analog to digital converter (ADC).

7. The balancing circuit of claim 6 , wherein the second circuit is operative during the first time period to select the one or more charged capacitors according to digital output signals from a stage ADC of the converter stage representing the amplitude of the input signal received by the converter stage during the first time period.

8. The balancing circuit of claim 2 , wherein the load circuit is a digital to analog converter (DAC) of the converter stage.

9. The balancing circuit of claim 1 , wherein the second circuit is operative during the first time period to select the one or more charged capacitors according to an amplitude of an input signal received by a converter stage of a pipeline analog to digital converter (ADC).

10. The balancing circuit of claim 9 , wherein the second circuit is operative during the first time period to select the one or more charged capacitors according to digital output signals from a stage ADC of the converter stage representing the amplitude of the input signal received by the converter stage during the first time period.

11. The balancing circuit of claim 1 , wherein the selected one or more capacitors are operative to provide charge to the output of the reference circuit during the second time period to offset loading of the load circuit.

12. A pipeline analog to digital converter (ADC), comprising:
a sample hold circuit to receive an analog input signal and including an output to provide a sample hold output signal representing a sample of the analog input signal;
a pipeline circuit including a converter stage, the converter stage including:
a stage input to receive an analog stage input signal from a preceding converter stage or from the sample hold circuit,
a stage digital output to provide a stage digital output signal,
a stage ADC circuit 200 to generate the stage digital output signal representing the analog stage input signal, and
a stage digital to analog converter (DAC), including a switched capacitor circuit, and an analog output to provide a stage analog signal representing the analog stage input signal according to a reference voltage signal and the stage digital output signal;

a reference circuit, including an output to provide the reference voltage signal to the stage DAC of the converter stage; and
a balancing circuit to balance a load of the reference circuit, the balancing circuit including:
capacitors,
a first circuit operative during a first time period to charge one or more of the capacitors using a voltage source, and
a second circuit operative during the first time period to select one or more of the charged capacitors according to an expected load of the stage DAC in a second time period,
the first circuit operative during the second time period to connect the selected one or more capacitors to the output of the reference circuit.

13. The pipeline ADC of claim 12 , wherein the voltage source has a voltage greater than the reference voltage signal.

14. The pipeline ADC of claim 12 , wherein the first circuit includes:
first switches to connect the one or more capacitors to the voltage source during the first time period, and to disconnect the one or more capacitors from the voltage source during the second time period; and
second switches individually associated with a corresponding one of the capacitors, the individual second switches operative when a corresponding control signal is in a first state to selectively connect the corresponding capacitor to the output of the reference circuit, and the individual second switches operative when the corresponding control signal is in a second state to disconnect the corresponding capacitor from the output of the reference circuit;
wherein the second circuit is operative during the first time period to provide the control signals in the second state to the second switches, wherein the second circuit is operative during the second time period to selectively provide the control signals in the first state to a selected set of the second switches corresponding to the selected one or more capacitors, and wherein the second circuit is operative during the second time period to selectively provide the control signals in the second state to any remaining unselected second switches.

15. The pipeline ADC of claim 12 , wherein the second circuit is operative during the first time period to select the one or more charged capacitors according to an amplitude of

Assignees

• Texas Instruments Inc

Inventors

• Francis Roswald
• Pentakota Visvesvaraya A

Classifications

• H03M1/167

  all stages comprising simultaneous converters (H03M1/165 takes precedence) · CPC title

• H03M1/0604 Primary

  at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/361

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title