Reference precharge techniques for analog-to-digital converters

Patent metadata

Field	Value
Publication number	US-10122376-B2
Application number	US-201715711176-A
Country	US
Kind code	B2
Filing date	Sep 21, 2017
Priority date	Nov 4, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Systems and methods to reduce the amount of reference current drawn by a SAR ADC by including an auxiliary or precharge reference source. The ADC can connect the bit trial capacitors of a main digital-to-analog converter (DAC) to an auxiliary or precharge reference source during the loading of the bit trials, and then the ADC can switch to a main reference buffer. After allowing enough time for both phases, the main DAC can proceed with the bit trials to resolve the remaining bits. The rest of the bit trials can be performed directly using the main reference buffer.

First claim

The claimed invention is:

1. A method of operating a successive approximation register (SAR) analog-to-digital converter (ADC) circuit to precharge a bit trial capacitor of a main ADC, the method comprising:
determining a bit trial result using an auxiliary ADC, the auxiliary ADC configured to resolve K bits of an N-bit digital word;
loading the bit trial result onto the bit trial capacitor of the main ADC;
connecting a first plate of the bit trial capacitor in the main ADC to a first reference voltage for a first time, the bit trial capacitor representing a bit of the K bits, the main ADC configured to resolve the remaining bits of the N-bit digital word; and
after the first time, disconnecting the first plate of the bit trial capacitor from the first reference voltage and connecting the first plate of the bit trial capacitor to a second reference voltage for a second time.

2. The method of claim 1 , wherein connecting the first plate of the bit trial capacitor in the main ADC to the first reference voltage for the first time, and wherein disconnecting the first plate of the bit trial capacitor from the first reference voltage and connecting the first plate of the bit trial capacitor to a second reference voltage for a second time includes:
if the bit trial result represents a “1” bit, connecting the first plate of the bit trial capacitor in the main ADC to a first positive reference voltage for a first time, and disconnecting the first plate of the bit trial capacitor from the first positive reference voltage and connecting the first plate of the bit trial capacitor to a second positive reference voltage for a second time; and
if the bit trial result represents a “0” bit, connecting the first plate of the bit trial capacitor in the main ADC to a first negative reference voltage for a first time, and disconnecting the first plate of the bit trial capacitor from the first negative reference voltage and connecting the first plate of the bit trial capacitor to a second negative reference voltage for a second time.

3. The method of claim 1 , wherein connecting the first plate of the bit trial capacitor in the main ADC to the first reference voltage for the first time includes:
connecting the first plate of the bit trial capacitor in the main ADC to a precharge reference buffer circuit for the first time, and
wherein connecting the first plate of the bit trial capacitor to the second reference voltage for the second time includes:
connecting the first plate of the bit trial capacitor to a main reference buffer circuit for the second time.

4. The method of claim 3 , wherein the precharge reference buffer circuit is less accurate than the main reference buffer circuit.

5. The method of claim 1 , wherein connecting the first plate of the bit trial capacitor in the main ADC to the first reference voltage includes:
connecting the first plate of the bit trial capacitor in the main ADC to a first reference voltage source for the first time, and
wherein connecting the first plate of the bit trial capacitor to the second reference voltage for the second time includes:
connecting the first plate of the bit trial capacitor to a second reference voltage source for the second time.

6. The method of claim 5 , wherein the first reference voltage source is less accurate than the second reference voltage source.

7. The method of claim 1 , wherein the SAR ADC includes a first channel and a second channel, wherein the bit trial result is a first bit trial result, wherein the first channel includes the auxiliary ADC and the main ADC, and wherein the second channel includes a second auxiliary ADC and a second main ADC, wherein the first channel and the second channel are configured to share the second reference voltage, wherein the first reference voltage includes a first positive reference voltage and a first negative reference voltage, wherein the second reference voltage includes a second positive reference voltage and a second negative reference voltage, and wherein the second reference voltage is more accurate than the first reference voltage, the method further comprising:
during a time at least partially overlapping with the determining, loading, connecting, disconnecting, and connecting of the first channel:
determining a second bit trial result using the second auxiliary ADC;
loading the second bit trial result determined using the second auxiliary ADC onto a bit trial capacitor in the second main ADC;
connecting a first plate of the bit trial capacitor in the second main ADC to one of the first positive reference voltage or the first negative reference voltage for the first time, based on the second bit trial result of the second auxiliary ADC; and
after the first time, disconnecting the first plate of the bit trial capacitor in the second main ADC from the first positive reference voltage or the first negative reference voltage and connecting the first plate of the bit trial capacitor in the second main ADC to one of the second positive reference voltage or the second negative reference voltage for the second time, based on the second bit trial result of second auxiliary ADC.

8. A successive approximation register (SAR) analog-to-digital converter (ADC) circuit for precharging a bit trial capacitor of a main ADC, the circuit comprising:
an auxiliary ADC configured to resolve K bits of an N-bit digital word;
a main ADC configured to resolve the remaining bits of the N-bit digital word, the main ADC including:
the bit trial capacitor representing a bit of the N-bit digital word;
first and second electronic switches coupled to a plate of the bit trial capacitor; and

control circuitry configured to:
determine a bit trial result using the auxiliary ADC;
load the at least one bit trial result onto the bit trial capacitor of the main ADC;
control the first electronic switch to connect the first plate of the bit trial capacitor of the main ADC to one of a first positive reference voltage or a first negative reference voltage for a first time based on the bit trial result of the auxiliary ADC; and
after the first time, control the first electronic switch to disconnect the first plate of the bit trial capacitor from the first positive reference voltage or the first negative reference voltage and control the second electronic switch to connect the first plate of the bit trial capacitor to one of a second positive reference voltage or a second negative reference voltage for a second time based on the bit trial result.

9. The circuit of claim 8 , wherein at least one of the first positive reference voltage and the first negative reference voltage includes a precharge reference buffer circuit.

10. The circuit of claim 9 , wherein at least one of the second positive reference voltage and the second negative reference voltage includes a main reference buffer circuit.

11. The circuit of claim 10 , wherein the precharge reference buffer circuit is less accurate than the main reference buffer circuit.

12. The circuit of claim 8 , wherein at least one of the first positive reference voltage and the first negative reference voltage includes a first reference voltage source.

13. The circuit of claim 12 , wherein at least one of the second positive reference voltage and the second negative reference voltage includes a second reference voltage source.

14. The circuit of claim 13 , wherein the first positive reference voltage is less accurate than the second positive reference voltage and the first negative reference voltage is less accurate than the second negative reference voltage.

15. The circuit of claim 8 , wherein the

Assignees

• Analog Devices Global

Inventors

• Kalathil Anoop Manissery
• Madan Arvind
• Monangi Sandeep

Classifications

• H03M1/145

  the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence) · CPC title

• H03M1/12 Primary

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title