Semiconductor device for improving transistor characteristics during turn-on

Patent metadata

Field	Value
Publication number	US-11264491-B2
Application number	US-202016940407-A
Country	US
Kind code	B2
Filing date	Jul 28, 2020
Priority date	Aug 10, 2018
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

Provided is a semiconductor device including a semiconductor substrate provided with a transistor portion, wherein the semiconductor substrate includes, in the transistor portion, a drift region of a first conductivity type; an accumulation region of the first conductivity type that has a higher doping concentration than the drift region; a collector region of a second conductivity type; and a plurality of gate trench portions and a plurality of dummy trench portions that are provided extending in a predetermined extension direction in the top surface of the semiconductor substrate, and are arranged in an arrangement direction orthogonal to the extension direction, and the transistor portion includes a first region that includes a gate trench portion; and a second region in which the number of dummy trench portions arranged in a unit length in the arrangement direction is greater than in the first region.

First claim

What is claimed is:

1. A semiconductor device comprising a semiconductor substrate provided with a transistor portion, wherein
the semiconductor substrate includes, in the transistor portion:
a drift region of a first conductivity type;
an accumulation region of the first conductivity type that is provided between the drift region and a top surface of the semiconductor substrate and has a higher doping concentration than the drift region;
a collector region of a second conductivity type that is provided between a bottom surface of the semiconductor substrate and the drift region; and
a plurality of gate trench portions and a plurality of dummy trench portions that are provided from the top surface of the semiconductor substrate to a position deeper than the accumulation region, the plurality of gate trench portions and the plurality of dummy trench portions extending in a predetermined extension direction in the top surface of the semiconductor substrate and arranged in an arrangement direction orthogonal to the extension direction,

the transistor portion includes:
a first region that includes a gate trench portion; and
a second region in which the number of dummy trench portions arranged in a unit length in the arrangement direction is greater than in the first region, and

the second region is arranged sandwiched by first regions, each first region being the first region, in the extension direction.

2. The semiconductor device according to claim 1 , wherein
the second region is arranged in a center of the transistor portion in the arrangement direction.

3. The semiconductor device according to claim 1 , wherein
the first region includes a plurality of gate trench portions, each gate trench portion being the gate trench portion, arranged continuously in the arrangement direction, but does not include the dummy trench portion.

4. The semiconductor device according to claim 1 , wherein
the second region includes both the dummy trench portion and the gate trench portion.

5. The semiconductor device according to claim 1 , wherein
the first region and the second region are arranged side by side in the arrangement direction.

6. The semiconductor device according to claim 1 , wherein
the first region and the second region are arranged side by side in the extension direction.

7. A semiconductor device comprising a semiconductor substrate provided with a transistor portion, wherein
the semiconductor substrate includes, in the transistor portion:
a drift region of a first conductivity type;
an accumulation region of the first conductivity type that is provided between the drift region and a top surface of the semiconductor substrate and has a higher doping concentration than the drift region;
a collector region of a second conductivity type that is provided between a bottom surface of the semiconductor substrate and the drift region; and
a plurality of gate trench portions and a plurality of dummy trench portions that are provided from the top surface of the semiconductor substrate to a position deeper than the accumulation region, the plurality of gate trench portions and the plurality of dummy trench portions extending in a predetermined extension direction in the top surface of the semiconductor substrate and arranged in an arrangement direction orthogonal to the extension direction,

the transistor portion includes:
a first region that includes a gate trench portion; and
a second region in which the number of dummy trench portions arranged in a unit length in the arrangement direction is greater than in the first region,

the semiconductor substrate is further provided with a diode portion,
a plurality of transistor portions, each transistor portion being the transistor portion, and a plurality of diode portions, each diode portion being the diode portion, are arranged in an alternating manner in the arrangement direction,
at least one of the transistor portions is not sandwiched by the diode portions in the arrangement direction,
at least one of the transistor portions is sandwiched by the diode portions in the arrangement direction, and
the second region of the transistor portion that is not sandwiched by the diode portions has a greater width in the arrangement direction than the second region of the transistor portion that is sandwiched by the diode portions.

8. A semiconductor device comprising a semiconductor substrate provided with a transistor portion, wherein
the semiconductor substrate includes, in the transistor portion:
a drift region of a first conductivity type;
an accumulation region of the first conductivity type that is provided between the drift region and a top surface of the semiconductor substrate and has a higher doping concentration than the drift region;
a collector region of a second conductivity type that is provided between a bottom surface of the semiconductor substrate and the drift region; and
a plurality of gate trench portions and a plurality of dummy trench portions that are provided from the top surface of the semiconductor substrate to a position deeper than the accumulation region, the plurality of gate trench portions and the plurality of dummy trench portions extending in a predetermined extension direction in the top surface of the semiconductor substrate and arranged in an arrangement direction orthogonal to the extension direction,

the transistor portion includes:
a first region that includes a gate trench portion; and
a second region in which the number of dummy trench portions arranged in a unit length in the arrangement direction is greater than in the first region,

the semiconductor substrate is further provided with a diode portion,
a plurality of transistor portions, each transistor portion being the transistor portion, and a plurality of diode portions, each diode portion being the diode portion, are arranged in an alternating manner in the arrangement direction, and
in the transistor portions, regions where a distance from the diode portions in the arrangement direction is greater have a higher ratio of the number of dummy trench portions to the number of gate trench portions.

9. The semiconductor device according to claim 1 , wherein
the second region is arranged sandwiched by the first regions also in the arrangement direction.

10. The semiconductor device according to claim 1 , wherein
the first region is arranged sandwiched by second regions, each second region being the second region, in both the extension direction and the arrangement direction.

11. The semiconductor device according to claim 1 , wherein
the first region is arranged sandwiched by second regions, each second region being the second region, in the extension direction.

12. The semiconductor device according to claim 1 , wherein
the first regions and second regions, each second region being the second region, are arranged in an alternating manner in the extension direction.

13. The semiconductor device according to claim 1 , wherein
the second region is surrounded by the first region in a top surface view.

14. The semiconductor device according to claim 1 , wherein
the first region is surrounded by the second region in a top surface view.

15. The semiconductor device according to claim 1 , wherein
the plurality of gate trench portions and the plurality of dummy trench portions are provided continuously in the extension direction from one of the first regions to another of the first regions through the second region.

Assignees

• Fuji Electric Co Ltd

Inventors

• Ozaki Daisuke
• KANETAKE Akinori
• SHIRAKAWA Tohru
• Sakurai Yosuke

Classifications

• H10D62/129

  Cathode regions of diodes · CPC title

• H10D84/617

  Combinations of vertical BJTs and only diodes · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D8/422

  PN diodes having the PN junctions in mesas · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title