Semiconductor device and manufacturing method for the same

Patent metadata

Field	Value
Publication number	US-9847409-B2
Application number	US-201514798712-A
Country	US
Kind code	B2
Filing date	Jul 14, 2015
Priority date	Jul 16, 2014
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A semiconductor device provides an element arrangement region on a semiconductor substrate including: a first semiconductor region on the semiconductor substrate; a second semiconductor region on the first semiconductor region; multiple trench gates penetrating the first semiconductor region and reaching the second semiconductor region; a third semiconductor region contacting the trench gate; a fourth semiconductor region on a rear surface; a first electrode connected to the first and second semiconductor regions; and a second electrode connected to the fourth semiconductor region. Each trench gate includes a main trench gate for generating a channel and a dummy trench gate for improving a withstand voltage of a component. The device further includes: a dummy gate wiring for applying a predetermined voltage to the dummy trench gate; and a dummy pad connected to the dummy gate wiring. The dummy pad and the first electrode are connected by a conductive member.

First claim

What is claim is:

1. A semiconductor device, comprising:
an element arrangement region on a main surface side of a semiconductor substrate, the element arrangement region including:
a first semiconductor region that is arranged in a surface portion of the semiconductor substrate at the main surface side;
a second semiconductor region that contacts the first semiconductor region and is arranged at a position deeper than the first semiconductor region;
a plurality of main trench gates that respectively penetrate the first semiconductor region and reach the second semiconductor region, and that respectively generate a channel by voltage application;
a plurality of dummy trench gates that respectively penetrate the first semiconductor region and reach the second semiconductor region, and respectively improve a withstand voltage of the semiconductor device without generating a channel;
a third semiconductor region that is arranged in the first semiconductor region to be in contact with each of the plurality of main trench gates;
a fourth semiconductor region that is arranged in a surface portion of the semiconductor substrate at a rear surface side opposite to the main surface side;
a first electrode that is arranged on the main surface of the semiconductor substrate and is electrically connected to the first semiconductor region and the second semiconductor region; and
a second electrode that is arranged on a rear surface of the semiconductor substrate and is electrically connected to the fourth semiconductor region,

the semiconductor device further comprising:
a dummy gate wiring that is arranged on the main surface of the semiconductor substrate for applying a predetermined voltage to each of the plurality of dummy trench gates;
a dummy pad that is connected electrically to the dummy gate wiring; and
a main gate pad that is connected to each of the plurality of main trench gates,

wherein the dummy pad and the first electrode are mutually connected electrically through a conductive member at the main surface side of the semiconductor substrate,
wherein the dummy pad and the main gate pad are arranged separately, and
wherein the dummy gate wiring is electrically isolated from the first electrode.

2. The semiconductor device according to claim 1 ,
wherein the dummy pad and the first electrode are mutually connected electrically by a bonding wire.

3. The semiconductor device according to claim 1 , further comprising:
a first lead frame that is arranged to overlap the dummy pad and the first electrode when it is viewed in a plan view from a thickness direction of the semiconductor substrate,
wherein the dummy pad and the first electrode are mutually connected electrically by the first lead frame.

4. The semiconductor device according to claim 1 ,
wherein the dummy pad is arranged to have a height identical to a height of the first electrode in the thickness direction of the semiconductor substrate.

5. The semiconductor device according to claim 1 ,
wherein the dummy pad is arranged in the element arrangement region when it is viewed in a plan view from the thickness direction of the semiconductor substrate.

Assignees

• Denso Corp

Inventors

• Shiga Tomofusa
• Tanabe Hiromitsu

Classifications

• H10W72/50

  Bond wires · CPC title

• H10W72/652

  comprising metals or metalloids, e.g. silver · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W72/5453

  connecting between multiple bond pads on a chip, e.g. daisy chain · CPC title