Method for forming film stacks with multiple planes of transistors having different transistor architectures

Patent metadata

Field	Value
Publication number	US-11264285-B2
Application number	US-201916665599-A
Country	US
Kind code	B2
Filing date	Oct 28, 2019
Priority date	Jul 8, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

Three-dimensional integration can overcome scaling limitations by increasing transistor density in volume rather than area. To provided gate-all-around field-effect-transistor devices with different threshold voltages and doping types on the same substrate, methods are provided for growing adjacent nanosheet stacks having channels with different doping profiles. In one example, a first nanosheet stack is formed having channels with first doping characteristics. Then the first nanosheet stack is etched, and a second nanosheet stack is formed in plane with the first nanosheet stack. The second nanosheet stack has channels with different doping characteristics. This process can be repeated for additional nanosheet stacks. In another example, the formation of the nanosheet stacks with channels having different doping characteristics is performed by restricting layer formation to predefined locations using a patterned layer (e.g., a conformal oxide layer) that limits epitaxial growth to exposed regions of the substrate where the patterned layer is etched away.

First claim

The invention claimed is:

1. A method of microfabrication, the method comprising:
forming a first nanosheet stack on a substrate, the first nanosheet stack having first layers of material including a semiconducting material, at least two of the first layers being first channels of gate-all-around (GAA) field-effect transistor (FET) devices, the first channels comprising a first channel material having a first doping profile;
masking a portion of the first nanosheet stack;
etching unmasked portions of the first nanosheet stack down to a predetermined depth; and
growing a second nanosheet stack on the substrate in regions of the substrate that have been etched, the second nanosheet stack being in plane with the first nanosheet stack, the second nanosheet stack having second layers of material including the semiconducting material, at least two of the second layers of material being second channels of GAA FET devices, the second channels comprising a second channel material having a second doping profile, the second doping profile causing the GAA FET devices of the second channels to have a different threshold voltage than the GAA FET devices of the first channels, wherein the step of forming the first nanosheet stack further includes that the first channels include at least four channels in which pairs of channels share common source/drain regions, such that one pair of channels forms a single GAA FET.

2. A method of microfabrication, the method comprising:
forming a first nanosheet stack on a substrate, the first nanosheet stack having first layers of material including a semiconducting material, at least two of the first layers being first channels of gate-all-around (GAA) field-effect transistor (FET) devices, the first channels comprising a first channel material having a first doping profile;
masking a portion of the first nanosheet stack;
etching unmasked portions of the first nanosheet stack down to a predetermined depth; and
growing a second nanosheet stack on the substrate in regions of the substrate that have been etched, the second nanosheet stack being in plane with the first nanosheet stack, the second nanosheet stack having second layers of material including the semiconducting material, at least two of the second layers of material being second channels of GAA FET devices, the second channels comprising a second channel material having a second doping profile, the second doping profile causing the GAA FET devices of the second channels to have a different threshold voltage than the GAA FET devices of the first channels,
wherein the step of growing the second nanosheet stack further includes that second channels have a channel dimension that is different than the first channels further causing the GAA FET devices of the second channels to have a different operating characteristic than the GAA FET devices of the first channels, the different operating characteristic being one of a capacitance, a current, a current-voltage curve, drive current saturation, mobility, off state leakage, and transconductance.

3. The method of claim 1 , wherein the first channels are doped using one of an n-type doping or a p-type doping and the second channels are doped using another of the n-type doping or the p-type doping, such that when the first channels have the p-type doping the second channels have the n-type doping and when the first channels have the n-type doping the second channels have the p-type doping.

4. The method of claim 1 , further comprising, prior to growing the second nanosheet stack, forming a conformal layer over the first nanosheet stack and then masking and etching the conformal layer to define the regions of the substrate that have been etched and in which the second nanosheet stack is grown.

5. The method of claim 1 , further comprising additional nanosheet stacks having additional channels comprising additional channel material, which have different doping profiles than the first channels and the second channels.

6. The method of claim 1 , wherein, in the step of growing the second nanosheet stack, the second channels are grown level with the first channels.

7. The method of claim 1 , further comprising creating GAA FET devices using the first channels and the second channels as GAA FET channels.

8. The method of claim 1 , further comprising, prior masking the portion of the first nanosheet stack, forming a cap layer on the first nanosheet stack.

9. The method of claim 1 , wherein the first nanosheet stack is epitaxially grown and the semiconducting material is silicon or is a III-V semiconductor.

10. The method of claim 1 , wherein the first channels are doped using a different dopant concentration than the second channels.

11. The method of claim 1 , wherein given layers of the first nanosheet stack are doped as individual layers are being grown.

12. A method of microfabrication, the method comprising:
forming a first mask on a substrate that defines a first region on the substrate, the first region being not covered by the first mask;
forming, in the first region, a first nanosheet stack on the substrate, the first nanosheet stack having first layers of material including a semiconducting material, at least two of the first layers being first channels of gate-all-around (GAA) field-effect transistor (FET) devices, the first channels comprising a first channel material having a first doping profile;
forming a second mask on the substrate that defines a second region on the substrate, the second mask covering the first nanosheet stack, and the second region being not covered by the second mask; and
forming a second nanosheet stack on the substrate in the second region, the second nanosheet stack being in plane with the first nanosheet stack, the second nanosheet stack having second layers of material including the semiconducting material, at least two of the second layers being second channels of GAA FET devices, the second channels comprising a second channel material having a second doping profile, the second doping profile causing the GAA FET devices of the second channels to have having a different threshold voltage than the GAA FET devices of the first channels, wherein the step of forming a first nanosheet stack further includes that the first channels include at least four channels in which pairs of channels share common source/drain regions, such that one pair of channels forms a single GAA FET.

13. The method of claim 12 , wherein the step of growing the second nanosheet stack further includes that second channels have a channel dimension that is different than the first channels further causing the GAA FET devices of the second channels to have a different operating characteristic than the GAA FET devices of the first channels, the operating characteristic being one of a capacitance, a current, and a current-voltage curve.

14. The method of claim 12 , wherein, in the first channels are doped using one of an n-type doping or a p-type doping and the second channels are doped using another of the n-type doping or the p-type doping, such that when the first channels have the p-type doping the second channels have the n-type doping and when the first channels have the n-type doping the second channels have the p-type doping.

15. The method of claim 12 , further comprising additional nanosheet stacks having additional channels comprising additional channel material, which have different doping profiles than the first channels and the second channels.

16. The method of claim 12 , wherein the first nanosheet stack is epitaxially grown and the semiconducting material is silicon

Assignees

• Tokyo Electron Ltd

Inventors

• Gardner Mark
• Fulford Jim

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title