Double-sided segmented line architecture in 3D integration

Patent metadata

Field	Value
Publication number	US-9559040-B2
Application number	US-201314143015-A
Country	US
Kind code	B2
Filing date	Dec 30, 2013
Priority date	Dec 30, 2013
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.

First claim

What is claimed is:

1. A method, comprising:
forming one or more intra-wafer through substrate vias (TSVs) extending from a front side of a substrate of a first integrated circuit (IC) chip to a back side of the substrate of the first IC chip;
forming a local architecture in a front side wiring layer of the first IC chip, the local architecture having one or more local features electrically connected to the one or more intra-wafer TSVs;
forming a global architecture in a back side wiring layer of the first IC chip, the global architecture connecting to the one or more intra-wafer TSVs and electrically coupling the one or more local features together;
bonding the first IC chip to a second IC chip, the second IC chip comprising a front side wiring layer and a back side wiring layer; and
forming one or more inter-wafer TSVs after bonding the first IC chip to the second IC chip, the one or more inter-wafer TSVs extending through an entire thickness of a periphery of the first IC chip and an entire thickness of a periphery of the second IC chip, the one or more inter-wafer TSVs electrically connecting the back side wiring layer of the second IC chip to the back side wiring layer of the first IC chip, the one or more inter-wafer TSVs having a width that is approximately n times larger than a width of the one or more intra-wafer TSVs, with the value of n being selected to reduce the number of repeaters required for distributing global signals, and n varying between approximately 8 and approximately 10.

2. The method of claim 1 , wherein forming the local architecture in the front side wiring layer of the first IC chip comprises:
forming a power gate switch.

3. The method of claim 1 , wherein forming the global architecture in the back side wiring layer of the first IC chip comprises:
connecting, electrically, the one or more inter-wafer TSVs to an external power source;
forming a power line connected to the one or more inter-wafer TSVs; and
forming a power bus line.

4. The method of claim 1 , wherein forming the local architecture in the front side wiring layer of the first IC chip comprises:
forming a PDL driver.

5. The method of claim 1 , wherein forming the global architecture in the back side wiring layer of the first IC chip comprises:
forming a PDL; and
forming a short back side wire connected to the one or more inter-wafer TSVs, the one or more inter-wafer TSVs electrically connected to an adjacent IC chip.

6. The method of claim 1 , wherein the local architecture includes a decoder that enables the one or more local features to connect to an individual wire in the global architecture using an individual intra-wafer TSV.

7. The method of claim 1 , wherein forming the global architecture in the back side wiring layer of the first IC chip comprises:
forming a power line bus connected directly to the one or more inter-wafer TSVs.

8. The method of claim 1 , wherein forming the global architecture in the back side wiring layer of the first IC chip comprises:
forming a PDL; and
forming a short back side wire connected to the one or more inter-wafer TSVs, the one or more inter-wafer TSVs electrically connected to a vertical stack of memory tiles on the front side.

9. A method, comprising:
forming one or more intra-wafer through substrate vias (TSVs) extending from a front side of a substrate of a first integrated circuit (IC) chip to a back side of the substrate of the first IC chip;
forming a local architecture in a front side wiring layer located on the front side of the substrate of the first IC chip, the local architecture having one or more local features electrically connected to the one or more intra-wafer TSVs;
bonding a second IC chip to the front side wiring layer of the first IC chip, the second IC chip comprising a front side wiring layer and a back side wiring layer;
forming a global architecture in a back side wiring layer located on the back side of the substrate of the first IC chip, the global architecture connecting to the one or more intra-wafer TSVs and electrically coupling the one or more local features together;
etching one or more recesses continuously through an entire thickness of both the first IC chip and the second IC chip, the one or more recesses being located along a periphery of both the first IC chip and the second IC chip; and
filling the one or more recesses with a conductive material to form one or more inter-wafer TSVs, the one or more inter-wafer TSVs electrically connecting the back side wiring layer of the second IC chip to the back side wiring layer of the first IC chip, the one or more inter-wafer TSVs having a width that is approximately n times larger than a width of the one or more intra-wafer TSVs.

10. A method, comprising:
forming one or more intra-wafer through substrate vias (TSVs) extending from a front side of a substrate of a first integrated circuit (IC) chip to a back side of the substrate of the first IC chip;
forming a local architecture in a front side wiring layer of the first IC chip, the local architecture having one or more local features electrically connected to the one or more intra-wafer TSVs;
bonding the first IC chip to a second IC chip, the second IC chip comprising a front side wiring layer and a back side wiring layer;
etching the back side of the substrate of the first IC chip to expose the one or more intra-wafer TSVs such that a conductive path exist through an entire thickness of the substrate of the first IC chip;
forming a global architecture in a back side wiring layer of the first IC chip, the global architecture connecting to the one or more intra-wafer TSVs and electrically coupling the one or more local features together;
etching one or more recesses continuously through an entire thickness of the first IC chip and through an entire thickness of the second IC chip, the one or more recesses being located along a periphery of both the first IC chip and the second IC chip; and
filling the one or more recesses with a conductive material to form one or more inter-wafer TSVs, the one or more inter-wafer TSVs electrically connecting the back side wiring layer of the second IC chip to the back side wiring layer of the first IC chip, the one or more inter-wafer TSVs having a width that is approximately n times larger than a width of the one or more intra-wafer TSVs, the value of n varying between approximately 8 and approximately 10.

Assignees

• IBM

Inventors

• Batra Pooja R
• Golz John W
• Jacunski Mark
• Kirihata Toshiaki

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title